cpu/esp8266: add RTT implementation #13640
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| include $(RIOTCPU)/esp_common/Makefile.features | ||
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| FEATURES_PROVIDED += arch_esp8266 | ||
| FEATURES_PROVIDED += periph_rtt | ||
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| /* | ||
| * Copyright (C) 2020 Gunar Schorcht | ||
| * | ||
| * This file is subject to the terms and conditions of the GNU Lesser | ||
| * General Public License v2.1. See the file LICENSE in the top level | ||
| * directory for more details. | ||
| */ | ||
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| /** | ||
| * @ingroup cpu_esp8266 | ||
| * @ingroup drivers_periph_rtt | ||
| * @{ | ||
| * | ||
| * @file | ||
| * @brief Low-level RTT driver implementation for ESP8266 | ||
| * | ||
| * @author Gunar Schorcht <gunar@schorcht.net> | ||
| * | ||
| * @} | ||
| */ | ||
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| #define ENABLE_DEBUG (0) | ||
| #include "debug.h" | ||
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| #include "cpu.h" | ||
| #include "log.h" | ||
| #include "periph/rtt.h" | ||
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| #include "esp/common_macros.h" | ||
| #include "esp/dport_regs.h" | ||
| #include "esp/rtc_regs.h" | ||
| #include "sdk/sdk.h" | ||
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| #define FRC2_CLK_DIV_256 2 /* divider for the 80 MHz AHB clock */ | ||
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| #define RTC_BSS_ATTR __attribute__((section(".rtc.bss"))) | ||
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| /** | ||
| * FRC2 is a 32-bit countup timer, triggers interrupt when reaches alarm value. | ||
| */ | ||
| typedef struct { | ||
| uint32_t load; | ||
| uint32_t count; | ||
| union { | ||
| struct { | ||
| uint32_t intr_hold : 1; | ||
| uint32_t reserved1 : 1; | ||
| uint32_t clk_div : 2; | ||
| uint32_t reserved2 : 2; | ||
| uint32_t reload : 1; | ||
| uint32_t enable : 1; | ||
| uint32_t intr_sta : 1; | ||
| uint32_t reserved3 : 23; | ||
| }; | ||
| uint32_t val; | ||
| } ctrl; | ||
| union { | ||
| struct { | ||
| uint32_t clear : 1; | ||
| uint32_t reserved1: 31; | ||
| }; | ||
| uint32_t val; | ||
| } intr; | ||
| uint32_t alarm; | ||
| } frc2_struct_t; | ||
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| /* | ||
| * linker script esp8266.peripherals.ld will make sure this points to the | ||
| * hardware register address | ||
| */ | ||
| extern volatile frc2_struct_t frc2; | ||
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| typedef struct { | ||
| uint32_t alarm; /**< alarm */ | ||
| rtt_cb_t alarm_cb; /**< alarm callback */ | ||
| rtt_cb_t overflow_cb; /**< overflow callback */ | ||
| void *alarm_arg; /**< argument for alarm callback */ | ||
| void *overflow_arg; /**< argument for overflow callback */ | ||
| } rtt_config_t; | ||
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| static rtt_config_t rtt_config; | ||
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| static uint32_t RTC_BSS_ATTR _rtt_counter_saved; | ||
| static uint32_t RTC_BSS_ATTR _rtc_counter_saved; | ||
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| extern uint32_t pm_rtc_clock_cali_proc(void); | ||
| extern uint32_t pm_rtc2usec(uint32_t rtc_cycles, uint32_t period); | ||
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| void rtt_restore_counter(void); | ||
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| void IRAM rtt_cb(void *arg) | ||
| { | ||
| /* triggered alarm */ | ||
| uint32_t alarm = frc2.alarm; | ||
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| if (alarm == rtt_config.alarm) { | ||
| rtt_cb_t alarm_cb = rtt_config.alarm_cb; | ||
| void * alarm_arg = rtt_config.alarm_arg; | ||
| /* clear the alarm first (includes setting next alarm to overflow) */ | ||
| rtt_clear_alarm(); | ||
| /* call the alarm handler afterwards if callback was defined*/ | ||
| if (alarm_cb) { | ||
| alarm_cb(alarm_arg); | ||
| } | ||
| } | ||
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benpicco marked this conversation as resolved.
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| if (alarm == 0) { | ||
| /* set next alarm which is either an alarm if configured or overflow */ | ||
| frc2.alarm = rtt_config.alarm; | ||
| /* call the overflow handler if configured */ | ||
| if (rtt_config.overflow_cb) { | ||
| rtt_config.overflow_cb(rtt_config.overflow_arg); | ||
| } | ||
| } | ||
| } | ||
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| void rtt_init(void) | ||
| { | ||
| DEBUG("%s saved rtt=%u rtc=%u\n", | ||
| __func__, _rtt_counter_saved, _rtc_counter_saved); | ||
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| frc2.ctrl.clk_div = FRC2_CLK_DIV_256; | ||
| frc2.ctrl.reload = 0; | ||
| frc2.ctrl.intr_hold = 0; | ||
| frc2.ctrl.enable = 1; | ||
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| /* initialize rtt_config structure after reboot or deep sleep */ | ||
| rtt_clear_alarm(); | ||
| rtt_clear_overflow_cb(); | ||
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| if (_rtt_counter_saved || _rtc_counter_saved) { | ||
| /* if not in init after power on, restore the RTT counter value */ | ||
| rtt_restore_counter(); | ||
| } | ||
| else { | ||
| frc2.load = 0; | ||
| DEBUG("%s after power on\n", __func__); | ||
| } | ||
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| /* emulate overflow interrupt */ | ||
| frc2.alarm = 0; | ||
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| ets_isr_attach (ETS_FRC2_INUM, rtt_cb, NULL); | ||
| ets_isr_unmask (BIT(ETS_FRC2_INUM)); | ||
| DPORT.INT_ENABLE |= DPORT_INT_ENABLE_FRC2; | ||
| } | ||
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| void rtt_poweron(void) | ||
| { | ||
| /* power on simply reactivates the FRC2 counter */ | ||
| frc2.ctrl.enable = 1; | ||
| } | ||
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| void rtt_poweroff(void) | ||
| { | ||
| /* power off simply deactivates the FRC2 counter */ | ||
| frc2.ctrl.enable = 0; | ||
| } | ||
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| void rtt_set_overflow_cb(rtt_cb_t cb, void *arg) | ||
| { | ||
| /* there is no overflow interrupt, we emulate */ | ||
| rtt_config.overflow_cb = cb; | ||
| rtt_config.overflow_arg = arg; | ||
| } | ||
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| void rtt_clear_overflow_cb(void) | ||
| { | ||
| /* there is no overflow interrupt, we emulate */ | ||
| rtt_config.overflow_cb = NULL; | ||
| rtt_config.overflow_arg = NULL; | ||
| } | ||
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| uint32_t rtt_get_counter(void) | ||
| { | ||
| return frc2.count; | ||
| } | ||
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| void rtt_set_counter(uint32_t counter) | ||
| { | ||
| frc2.load = counter; | ||
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benpicco marked this conversation as resolved.
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| if (counter > frc2.alarm) { | ||
| /* overflow is the next interrupt event */ | ||
| frc2.alarm = 0; | ||
| } | ||
| } | ||
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| void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg) | ||
| { | ||
| rtt_config.alarm = alarm; | ||
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Contributor
There was a problem hiding this comment.
e.g.
Contributor
Author
There was a problem hiding this comment. Indeed. It requires also to change the interrupt handling in BTW, configured alarms will not survive deep sleep and reboots. Otherwise the whole
Contributor
Author
There was a problem hiding this comment. OK, seems to work now: Because of the interrupt latency, the only case that cannot be handled with this emulated overflow interrupt is when the alarm is set to 0.
Contributor
There was a problem hiding this comment.
But if you can set an overflow 'alarm' you can also set an alarm at 0, they should happen at the same time.
Contributor
Author
There was a problem hiding this comment. @benpicco Thanks for your suggestions. I had simpler solution already
Contributor
Author
There was a problem hiding this comment. My problem was that I tried to test the current counter value, which of course can be larger than the configured alarm value due to the interrupt latency. So the solution was not to test the actual counter value but the configured alarm value. Since |
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| rtt_config.alarm_cb = cb; | ||
| rtt_config.alarm_arg = arg; | ||
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| if (frc2.count < alarm) { | ||
| frc2.alarm = alarm; | ||
| } | ||
| } | ||
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| uint32_t rtt_get_alarm(void) | ||
| { | ||
| return rtt_config.alarm; | ||
| } | ||
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| void rtt_clear_alarm(void) | ||
| { | ||
| frc2.alarm = 0; | ||
| rtt_config.alarm = 0; | ||
| rtt_config.alarm_cb = NULL; | ||
| rtt_config.alarm_arg = NULL; | ||
| } | ||
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| void rtt_save_counter(void) | ||
| { | ||
| /* save counters before going to sleep or reboot */ | ||
| _rtt_counter_saved = frc2.count; | ||
| _rtc_counter_saved = RTC.COUNTER; | ||
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Contributor
There was a problem hiding this comment. Where does
Contributor
Author
There was a problem hiding this comment. In contrast to all other peripherals for which the SDK defines the registers as a struct, the registers of the RTC module aren't defined by the SDK at all, see rtc_register.h. Therefore, another piece of vendor code is used which was initially extracted from the esp-open-rtos. It tries to define the RTC registers as a struct. BTW, this struct is defined exactly in the way you mentioned with volatile members and without linker stuff. ESP8266 is a terrible platform. It has the worst documentation I have ever seen and there is no consistent development environment. |
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| DEBUG("%s saved rtt=%u rtc=%u\n", | ||
| __func__, _rtt_counter_saved, _rtc_counter_saved); | ||
| } | ||
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| void rtt_restore_counter(void) | ||
| { | ||
| uint32_t rtc_diff = RTC.COUNTER - _rtc_counter_saved; | ||
| uint32_t rtc_diff_us = pm_rtc2usec(rtc_diff, pm_rtc_clock_cali_proc()); | ||
| uint32_t rtt_diff = RTT_US_TO_TICKS(rtc_diff_us); | ||
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| frc2.load = _rtt_counter_saved + rtt_diff; | ||
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| DEBUG("%s rtc_diff=%u rtt_diff=%u load=%u\n", __func__, | ||
| rtc_diff, rtt_diff, _rtt_counter_saved + rtt_diff); | ||
| } | ||
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