SPI PROTOCOL VERIFICATION USING SYSTEM VERILOG

Created SPI master and slave RTL in SystemVerilog using 3-wires (MOSI, SCLK, CS). Developed a class-based layered verification environment testbench to verify accurate serial data transfer.

CONTENTS

• INTRODUCTION
  • What is SPI?
  • Why SPI?
• DESIGN SPECIFICATION
• BLOCK DIAGRAM
• SPI MASTER
  • Signals
• SPI SLAVE
  • Signals
• WORKING
  • Serial clock (sclk)
  • Chip Select signal (cs)
  • MOSI
• FLOWCHART
  • Serial Clock Generation
• SV FILES
• RESULTS
  • Simulation Waveform
  • Console Output
• TOOLS USED

• EDA Playground Link

INTRODUCTION

What is SPI?

SPI stands for Serial Peripheral Interface, originally developed by Motorola. It is a synchronous serial communication protocol, meaning data transfer is aligned with the edges of a clock. It uses four main signals — MOSI, MISO, SCLK, and Chip Select — to enable communication between a master, usually a microcontroller, and slave devices such as ADCs, DACs, sensors, EEPROMs, or displays. SPI supports full-duplex transfer, so data can be sent and received simultaneously. Because it is simple, fast, and flexible, it is very popular in embedded systems and digital communication applications.

Why SPI?

SPI is used because it’s simple, fast, and efficient for short-distance communication. It supports full-duplex data transfer, meaning data can be sent and received at the same time. One unique benefit of SPI is the fact that data can be transferred without interruption. Any number of bits can be sent or received in a continuous stream. With I2C and UART, data is sent in packets, limited to a specific number of bits. Start and stop conditions define the beginning and end of each packet, so the data is interrupted during transmission. The trade-off is that it requires more pins, especially if multiple slaves are connected, but in cases where speed and simplicity are more important, SPI is usually preferred.

DESIGN SPECIFICATION

BLOCK DIAGRAM

In our design we do not have MISO (Master In Slave Out) signal as only master transmits the data and the slave reads it.

SPI MASTER

Signals

NAME	TYPE	DESCRIPTION
clk	Input	The main system clock.
rst	Input	Active low reset signal.
newd	Input	control signals that goes high when new data is to be transmitted via SPI.
din	Input	12 bit data input.
cs	Output	Chip select signal for selecting slave. It is active low when transmitting data.
mosi	Output	Master out Slave In - used to transmit data serially from master to slave.
sclk	Output	Serial clock that synchronizes with slave.

SPI SLAVE

Signals

NAME	TYPE	DESCRIPTION
cs	Input	Chip select signal for selecting slave. It is active low when transmitting data.
mosi	Input	Master out Slave In - used to receive data serially from master.
sclk	Input	Serial clock that synchronizes with master.
dout	Output	12 bit data out.
done	Output	Indicates that the data is received by slave

WORKING

Serial clock (sclk)

• The clock signal sclk is generated by the master. Slaves do not require their own clocks, even when they are transmitting data to master.
• Speed usually in MHz range -- usually fater than UART or I2C.
• The clock signal synchronizes the output of data bits from the master to the sampling of bits by the slave.
• One bit of data is transferred in each clock cycle, so the speed of data transfer is determined by the frequency of the clock signal.
• SPI communication is always initiated by the master since the master configures and generates the clock signal.
• Clock can be idle low or idle high. (In our design, it is idle low)
• Data can be sampled at positive or negative edge of clock.

Chip Select signal (cs)

• Also called 'Slave Select' (ss).
• The master can choose which slave it wants to talk to by setting the slave’s CS/SS line to a low voltage level.
• Then, the slave listens for sclk and mosi.
• In the idle, non-transmitting state, the slave select line is kept at a high voltage level.
• Multiple CS/SS pins may be available on the master, which allows for multiple slaves to be wired in parallel. (we only have 1 slave in our design)

MOSI

• The master sends data to the slave bit by bit, in serial through the MOSI line.
• The slave receives the data sent from the master at the MOSI pin.
• Data sent from the master to the slave is usually sent with the most significant bit first.

FLOWCHART

1. If newd signal is HIGH, start sampling the data on din bus and start transmitting it to slave device.
2. cs = 1 (default value); no transmission
3. cs = 0 ; transmission start
4. sclk is usually 4 times slower than system clock. This may differ for different FPGA boards.
5. In our design, random count (divide by 20) is used for generating serial clock.

Serial Clock Generation

System clock = Fclk
SPI clock = Fsclk
Fsclk = Fclk / 20 (divide by 20)
=> Tsclk = 20*Tclk
Therefore, sclk is on for 10xTclk and off for 10xTclk

SV FILES

├── spi_top.sv
│   ├── spi_master.sv
│   ├── spi_slave.sv
├── simple_tb.sv
├── test.sv

• simple_tb.sv is a simple Verilog testbench to verify the functionality.
• test.sv is a System Verilog class-based testbench verification environment to verify the bit by bit serial data transfer.

RESULTS

Simulation Waveform

Console Output

TOOLS USED

• EDA Playground
• Xilinx Vivado

EDA Playground Link

SPI Protocol