🚀 UART Protocol with FIFO Buffers

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📝 Overview

A Verilog-based UART (Universal Asynchronous Receiver/Transmitter) design integrated with FIFO buffers to enable efficient and reliable serial communication between devices.

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📖 What is UART?

UART (Universal Asynchronous Receiver/Transmitter) is a hardware protocol for serial communication, transmitting and receiving data one bit at a time.
It is asynchronous, meaning the transmitter and receiver do not share a clock, but agree on a baud rate to interpret data correctly.

✅ Key Points:

• 🔄 Converts parallel data to serial and vice versa.
• 🟢 Uses start and stop bits for synchronization.
• ↔️ Supports full-duplex communication.
• 💻 Commonly used in microcontrollers, FPGAs, PCs, and peripherals.

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❓ Why and Where is UART Used?

• Why: ⚡ Simple, cost-effective, and reliable for short distances.
• Where: 🔗 Communication between microcontrollers, FPGA boards, PCs, sensors, GPS modules, Bluetooth devices, ADCs, etc.

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⏱ Working with 16× Oversampling

• 🔍 Receiver samples the incoming data 16 times per bit period.
• 🎯 Detects the middle of each bit, reducing timing errors.
• 📊 Example: For 9600 bps, the sampling clock runs at 9600 × 16 = 153600 Hz.
• Process: Start bit detection → sample data bits at 16× rate → stop bit verification.

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✨ Features

🔹 UART Features

• 📡 Asynchronous serial communication.
• ↔️ Full-duplex support.
• ⚙️ Configurable data frame of 5–8 data bits, parity, 1–2 stop bits (Here, 8 data bits, no parity, 1 stop bit)
• 🛠 Simple hardware implementation.
• ✅ Reliable for short distances.
• 📏 Configurable baud rate.
• ⚠️ Supports error detection.
• 🌍 Widely supported in embedded systems.

🔸 FIFO Features

• 📥 First-In-First-Out data handling.
• ⏳ Temporary data storage between producer and consumer.
• 🔄 Smooth operation in full-duplex systems.
• 📐 Configurable depth and width.
• 🚦 Status signals: full, almost full, empty, almost empty.
• 🛡 Reduces data loss during bursts.
• ⚡ Hardware-friendly design for FPGA/ASIC systems.

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🧰 Working

The serial transmission starts with a 'start bit' (0), followed by data bits (1 byte), and ends with a 'stop bit'.

📌 Transmission of a single byte:

Since the transfer is asynchronous, the receiver and transmitter must agree on baud rate, stop bits, and parity bit.

📊 Using 16× oversampling, the middle of the data bit is estimated for accuracy:

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🏗 Design Details

⚡ Configuration Table

Parameter	Value
Data Bits	8
Stop Bits	1
Parity	None
Oversampling	16×
Baud Rate	9600

📌 Block Diagram

📤 Transmitter ASMD Chart

📥 Receiver ASMD Chart

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📂 Directory Structure

├── uart.v # Top-level UART module
├── uart_tx.v # UART transmitter
├── uart_rx.v # UART receiver
├── fifo.v # FIFO buffer module
├── uart_tb.v # UART testbench
├── fifo_tb.v # FIFO testbench
└── README.md # Project documentation

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⚙️ Module Details

• uart.v → Integrates UART transmitter, receiver, and FIFO.
• uart_tx.v → Handles serial data transmission.
• uart_rx.v → Handles serial data reception.
• fifo.v → Manages data buffering between TX and RX.
• uart_tb.v & fifo_tb.v → Testbenches for simulation and verification.

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💻 Simulation

📌 Requirements

• Simulator: ModelSim, Vivado Simulator, or any Verilog-compatible tool.
• FPGA Tool: Quartus, Vivado, or any synthesis tool for FPGA deployment.

▶️ Simulation Steps

1. Compile all Verilog modules and testbenches.
2. Load testbenches into the simulator.
3. Run simulation and verify waveforms for correct data transfer.

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📐 Schematic

🖼 RTL Schematic

🖼 Synthesis Schematic

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📊 Results

🔹 UART Top

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🔹 UART Transmitter

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🔹 UART Receiver

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🏆 Tools Used

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📜 License

📌 This project is licensed under the MIT License.

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🤝 Contribution

Contributions are welcome! 🎉

If you’d like to improve this project (bug fixes, feature enhancements, documentation, etc.), follow these steps:

1. 🍴 Fork the repository.
2. 🌱 Create a new branch:

   git checkout -b feature-name
   git commit -m "Add new feature or fix bug"
   git push origin feature-name