"Turning ISA specifications into silicon."
🎓 Electronics & Communication Engineering Undergraduate at College of Engineering Guindy (Anna University)
💻 Focused on
- RTL Design
- Computer Architecture
- ASIC Design Flow
- RISC-V Processor Design
- Physical Design
- Open-Source Silicon
Currently building a 32-bit RV32I Processor completely from scratch, while exploring the complete RTL → GDSII flow using open-source EDA tools.
Designing a complete 32-bit RV32I Processor from scratch.
- Program Counter
- Instruction Memory
- Register File
- ALU
- Immediate Generator
- Control Unit
- Branch Logic
- Data Memory
- Datapath Integration
Next Goals
- Pipeline implementation
- Hazard Detection
- Forwarding Unit
- Performance Analysis
✔ 8-bit Signed Booth Multiplier
✔ 16-bit Carry Lookahead Adder
✔ FPGA synthesis using Vivado
✔ RTL → GDSII using
- Yosys
- OpenLane
- Sky130
- Cadence Genus
- Innovus
Tiny Tapeout Sky25A Shuttle
Highlights
- Clock Domain Crossing
- Gray Code Pointers
- Two-Flip-Flop Synchronizers
- RTL Verification
- RTL → GDSII Implementation
CEG Fabless Initiative × SHAKTI Processor Group (IIT Madras) × Vyoma Systems
Worked on
- RISC-V ISA
- Assembly Programming
- Cache Replacement Policies
- RTL Development
- Functional Verification
- Processor Pipelining
- Static Timing Analysis
- Physical Design
- Advanced SystemVerilog
- Computer Architecture
🏅 Reliance Foundation Undergraduate Scholar
🏅 NPTEL — Digital IC Design
🏅 NPTEL — Embedded Systems Design
🏅 NPTEL — RTL to GDSII Design Flow
