CMOS-Inverter-Characterization-

Comprehensive CMOS inverter characterization including VTC, noise margins, delay, rise/fall times, power analysis, and parameter sweeps using NGSpice

For line width and color in NGSpice -

set color0=white --> Defines color0 as white. color0 is typically used for the background in waveforms/plots. So this sets the waveform window background to white.

set color1=black --> Defines color1 as black. Usually, color1 is used for grid lines or axes.

set color2=red --> Defines color2 as red. This color will be used for plotting the first waveform trace.

Set color3=blue --> Defines color3 as blue. This color is used for the second waveform trace.

(Similarly, more colors can be defined for other traces if needed.)

set xbrushwidth=3 --> Sets the brush width (line thickness) of waveforms to 3. This makes plotted traces thicker, which helps visibility.

For Rise and fall time -

T_rise → the name of the measurement (SPICE will store result in this variable). trig v(out) val = 0.1supply rise = 1 means "Start timing when v(out) crosses 10% of VDD on a rising edge." rise=1 means use the first rising crossing. targ v(out) val = 0.9supply rise = 1 means "Stop timing when v(out) crosses 90% of VDD on the same rising edge."

T_fall = the measured fall time. Trigger: When v(out) crosses 90% VDD on a falling edge (fall=1). Target: When v(out) crosses 10% VDD on the same falling edge.

For Rise time -

Trigger: trig = 1.002941e-08 s → the instant when v(out) crossed 0.1·VDD on a rising edge.

Target: targ = 1.004662e-08 s → the instant when v(out) crossed 0.9·VDD on that same rising edge.

✅ So the inverter output took 17.2 ps to rise from 10% to 90% of VDD.

For propogation delay -

For Noise margin do DC analysis (File given in repository ) -

Add this line -

For Power -

Code is In folder cmos inverter VTC curve

For pmos size variation -

dc1.out indicates wp = 10u , dc2.out indicates wp = 20u , dc3.out indicates wp = 30u

This means by increasing width of pmos in cmos inverter, the vtc curve will go towards right.

For Nmos size variation -

This means by increasing width of nmos in cmos inverter, the vtc curve will go towards left as above.

Red = 10u, blue = 20u , green = 30u

For length variation -

foreach len 0.2u 0.5u 1u

alter m1 l =$len

**Effect of supply voltage :- **

Noise margin analysis -

Delay, Rise time and fall time -

Power and energy -

Effect on Vm -

We can notice that If PMOS width is small or PMOS is weaker. NMOS dominates → inverter pulls down earlier → Vm shifts lower.

If PMOS width is increased, PMOS gets stronger. PMOS resists the NMOS pull-down → Vm shifts higher. VTC curve sgift right side

NOTE:- All analysis is done on pmos width variation similarly we can vary n mos size and do the analysis.

Effect of load capacitance on time-

**Effect of load capacitance on noise margin - **

Above we can see that Noise margin, VOH, VIL, etc. → unaffected by load capacitance.

Delay, rise/fall time, power → strongly affected by load capacitance

Larger load capaictance → slower output transitions, more delay, more power.

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For any query email on sanjeen598@gmail.com