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  • Delhi University Faculty of Technology
  • Delhi
  • 00:22 (UTC +05:30)

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Achievement: Pull SharkAchievement: YOLO

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Shreyasilver22/README.md

Shreyas Singh

Analog / Digital IC Design · RISC-V · FPGA Systems

RTL → Layout → Silicon

LinkedIn Email GitHub


About

B.Tech ECE (VLSI) at the Faculty of Technology, University of Delhi — 8th rank in department. I work across the stack: transistor-level analog design, RTL and FPGA prototyping, and system architecture. Most of what's below started as a datasheet, a simulation that didn't converge, or a spec that didn't quite make sense until I built it.

Currently: designing a two-stage Miller-compensated OTA,an SPI block and a switched-capacitor CDS front-end for a capacitive pressure sensor ASIC, as part of the 2026 IEEE SSCS Open-Source Chipathon.


Projects

Dual-Mode Edge-AI RV32I SoC Custom 5-stage RISC-V core with a dual-mode AI accelerator dispatched through a custom opcode. 7.0× speedup over baseline, <3.5% LUT utilization on a Zynq 7020, validated on physical silicon with Xilinx ILA.

Verilog Vivado PYNQ-Z2 Repo →

Low-Power NN Accelerator MNIST inference IP core on Artix-7 — 84% accuracy at 0.243 W. Built for the constraint, not around it.

Verilog Artix-7 Vivado Repo →

6T SRAM & Digital Cell Library Full-custom floorplanning, DRC/LVS/RC extraction on standard logic gates; area- and stability-optimized 6T SRAM cell.

Cadence Virtuoso L-Edit Repo →

Current-Mode VLSI Circuits Translinear circuits, OMAs, CFOAs and CCIIs — multi-corner analysis demonstrating gain-bandwidth decoupling for high-frequency stability.

SPICE Translinear Design Repo →

Exotic Semiconductor Modeling TCAD models of MOSFETs, FDSOI, and BJTs; electrothermal analysis of short-channel effects and DIBL.

Silvaco TCAD Repo →

Research & Industry

IEEE MAPCON 2025 — Co-authored a paper on high-gain sub-6 GHz antenna design during a research internship at CSIR-CSIO. The redesign closed a gain limitation in the existing literature model: +1.38 dB gain, 2× bandwidth (230 MHz), simulated in HFSS and CST Studio.

USICT IDEA Lab — IoT-based automatic irrigation system: soil moisture sensing, ESP32, solenoid actuation, Blynk telemetry.


Toolchain
Languages Verilog · SystemVerilog · C/C++ · Python · MATLAB
Analog / Layout Cadence Virtuoso · Silvaco TCAD · L-Edit · LTSpice
Digital / FPGA Xilinx Vivado · RTL Design · AXI · I2C
RF / EM Ansys HFSS · CST Studio
ML PyTorch · TensorFlow · Scikit-learn · OpenCV

Elsewhere

Director of Technical Activities, IEEE Student Chapter — ran LineTrek, a line-follower robotics tournament, under Astraaya. Occasional MUN delegate. AI HARDWARE ATTACK CHALLENGE @ IEEE DAC 2026, FINALIST, Chipmonk Hackathon (SAKEC Mumbai) Top 10, GGSIPU Delhi Ideathon Top 20/100+.



Gain, bandwidth, power — pick your trade-offs carefully.

Pinned Loading

  1. Digital-PID-controller-for-HOTPLATE Digital-PID-controller-for-HOTPLATE Public

    This repository is for the case study project done in DSC-14 Control Systems for B.Tech degree at Faculty of Technology, University of Delhi. It involves creating a PID controller but combing the p…

    Verilog 1

  2. Neural-Accelerator Neural-Accelerator Public

    This repository is related to the work done under the SEC project done in 5th semester by me

    Verilog 1 1

  3. Neural_Network_Hybrid_Optimizer-NNHO2025- Neural_Network_Hybrid_Optimizer-NNHO2025- Public

    A PyTorch implementation of a novel Hybrid Optimizer combining RMSProp with Particle Swarm Optimization (PSO). Achieves Adam-level performance on CIFAR-10 through dynamic swarm annealing and moment…

  4. RV32I-CPU-CORE-with-Custom-SCNN-acceleration RV32I-CPU-CORE-with-Custom-SCNN-acceleration Public

    This repository is related to the workd done for Sakec Hackathon 2026

    Verilog 1

  5. VLSI_Portfolio_Cadence_Analog_Digital_IC_Design VLSI_Portfolio_Cadence_Analog_Digital_IC_Design Public

    This repository contains all the designs done by Shreyas Singh in the VLSI related Labs-Digital VLSI design(5th semester) and Current Mode Analog VLSI desig(6th sem)

    1

  6. OCCPSense_Capacitive_Pressure_Sensor OCCPSense_Capacitive_Pressure_Sensor Public

    Low-Power Mixed-Signal Readout Chain for Capacitive Sensor Interface An ultra-low-power, self-calibrating Capacitance-to-Digital Converter (CDC) Readout IC targeting the 2026 SSCS Open-Source Chipa…

    Verilog 1