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1. Low-Power-Low-Noise-CMOS-ECG-Front-End-IC Low-Power-Low-Noise-CMOS-ECG-Front-End-IC Public

   Complete design, Cadence Spectre SPICE netlists, transistor sizing specs, architectural documentation, and Python analytical verification models for a Low-Power, Low-Noise CMOS Analog Front-End (AF…

   1

2. In-Memory-Computing-Applied-on-an-8x8-6T-SRAM-Array In-Memory-Computing-Applied-on-an-8x8-6T-SRAM-Array Public

   Comparative VLSI design, layout, and simulation of an 8×8 6T SRAM cell array with embedded In-Memory Computing (IMC) capabilities across 180 nm, 90 nm, and 45 nm CMOS technology libraries in Cadenc…

3. Reconfigurable-Systolic-Array-Multiplier Reconfigurable-Systolic-Array-Multiplier Public

   A fully synthesizable, parameterized Reconfigurable 64x64 Systolic Array Multiplier in Verilog with dynamic allocation capability ( 1 ≤ N ≤ 64 ).

   Verilog

4. Optimised-Recursive-FM-Algorithm-and-Graphical-Representation Optimised-Recursive-FM-Algorithm-and-Graphical-Representation Public

   This repository provides an extended, multi-branched, area-constrained, recursive, and randomized FM partitioning tool for digital Verilog netlists

   Python

5. 3D-Tunneling-FET-DGTFET- 3D-Tunneling-FET-DGTFET- Public

   complete quantum mechanical modeling framework and Synopsys Sentaurus TCAD simulation suite for a sub-10 nm 3D Double-Gate Tunnel Field-Effect Transistor (DGTFET)

   Scheme

6. Physical-Design-Implementation-of-Serial-Peripheral-Interface-Internship- Physical-Design-Implementation-of-Serial-Peripheral-Interface-Internship- Public

   End-to-end Digital ASIC Physical Design Implementation (RTL-to-GDSII) of a Serial Peripheral Interface (SPI) core using the open-source QFLOW EDA toolchain (Yosys, Graywolf, Qrouter, OpenSTA, Magic…

   Verilog