Name		Name	Last commit message	Last commit date
2bit_2to_1 _MUX		2bit_2to_1 _MUX
4-bit_ripple_carry_adder		4-bit_ripple_carry_adder
4bit_reg		4bit_reg
A5_1		A5_1
A_5		A_5
A_5_1_100		A_5_1_100
A_5_1_55		A_5_1_55
A_5_1_62		A_5_1_62
A_5_1_66		A_5_1_66
A_5_1_6_a		A_5_1_6_a
A_5_1_6_b		A_5_1_6_b
A_5_1_90		A_5_1_90
A_5_1_95		A_5_1_95
A_5_2_2		A_5_2_2
A_5_2_2_100		A_5_2_2_100
A_5_2_2_105		A_5_2_2_105
A_5_2_2_111		A_5_2_2_111
A_5_2_2_127		A_5_2_2_127
A_5_2_2_83		A_5_2_2_83
A_5_2_4		A_5_2_4
A_5_2_4_166		A_5_2_4_166
A_5_2_4_200		A_5_2_4_200
A_5_2_4_250		A_5_2_4_250
A_5_2_4_266		A_5_2_4_266
A_5_2_4_277		A_5_2_4_277
A_5_2_4_280		A_5_2_4_280
Asign_4_1_LFSR_internal		Asign_4_1_LFSR_internal
Assign_4_1_LFSR_external		Assign_4_1_LFSR_external
Assign_4_2		Assign_4_2
Assign_4_3_FIR_Filter		Assign_4_3_FIR_Filter
Assign_4_4_FIR_Para		Assign_4_4_FIR_Para
Assign_test		Assign_test
Assignment3_Q2		Assignment3_Q2
Assignment_3		Assignment_3
Block_RAM		Block_RAM
Case_1		Case_1
DFF_AsyR		DFF_AsyR
DFF_for_loop		DFF_for_loop
DFlipFlop_Syn_reset		DFlipFlop_Syn_reset
DMUX		DMUX
D_flip_flope		D_flip_flope
D_latch		D_latch
D_latch_asynchronous_reset		D_latch_asynchronous_reset
FIR_IP		FIR_IP
FSM_Test		FSM_Test
Full_adder		Full_adder
H1		H1
H2		H2
H3		H3
H4		H4
Initial		Initial
LFSR		LFSR
Matlab work		Matlab work
Parameterized_LFSR		Parameterized_LFSR
Project		Project
Register		Register
bit_serial_adder		bit_serial_adder
conditional_operater		conditional_operater
decoder		decoder
decoder_for		decoder_for
encoder		encoder
fixed point mulitplication using ip		fixed point mulitplication using ip
ip		ip
multiplexer_2to1_MUX		multiplexer_2to1_MUX
multiplexer_with_case		multiplexer_with_case
mux_with_for_loop		mux_with_for_loop
perameterized_mux		perameterized_mux
project_1assigment		project_1assigment
LICENSE		LICENSE
Project.rar		Project.rar
README.md		README.md

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