[ENG-1969] Resim each instance independently

[hsiang20]

Summary

Extend sim to support boundary-cut, multi-root co-simulation so a single FST/VCD can be replayed in parallel. Activity-factor capture also gains a clock-period override for workers that only see a partial design.

Changes

• Added -bb to cut every parent↔child boundary and source both sides from the FST; skips parent→child input copies and parent output pull-ups, and feeds each child's port inputs from VCD handles.
• Added -instance <module>:<scope> (repeatable) to root one SimInstance
  per spec instead of recursing from the design top.
• Added -clk-period <seconds> to bypass the highest-toggling-signal heuristic when computing activity-factor frequency.
• Generalized SimWorker from a single top to a tops vector.

[linear]

ENG-1969

[greptile-apps]

Greptile Summary

This PR extends the sim pass with three new flags (-bb, -instance, -clk-period) that enable boundary-cut, multi-root co-simulation from a single FST/VCD, and generalises SimWorker from a single top pointer to a tops vector so multiple SimInstance roots can be driven in parallel.

• -bb: cuts every parent↔child module boundary; child outputs are sourced from the FST rather than driven by the parent, enabling each root to simulate its own logic in isolation.
• -instance <module>:<scope> (repeatable): directly roots a SimInstance at the named module/scope, bypassing design-top traversal; requires FST cosim.
• -clk-period <seconds>: overrides the highest-toggling-signal heuristic used by AnnotateActivity to compute clock frequency, which is otherwise unreliable when a worker sees only a partial design.

Confidence Score: 4/5

Safe to merge after fixing the null-pointer dereference in sim_cell_unevaluated; all other paths in the new multi-root logic are correctly guarded.

The new -bb guard in sim_cell_unevaluated dereferences mod->name without a null check. Any cell whose type is absent from the design will crash the simulator in -bb mode rather than emitting the existing log_error. That is a real, reproducible crash on any design containing external or library cells not loaded into the current Yosys session. The rest of the multi-root plumbing looks correctly handled.

passes/sat/sim.cc — specifically the new guard block added inside sim_cell_unevaluated around line 652.

Important Files Changed

Filename	Overview
passes/sat/sim.cc	Adds -bb, -instance, and -clk-period flags; generalises SimWorker from a single top to a tops vector. Contains a null-pointer dereference in sim_cell_unevaluated when -bb is active and a cell's type is not present in the design.

_{Reviews (2): Last reviewed commit: "chore: add comments and log" | Re-trigger Greptile}

[hsiang20]

@greptile could you review again