[ENG-1992] Activity-based clock gating

[stanminlee]

Modified clockgate pass to allow for a new option, where we can gate flops based on inferred enable duty cycle

Algorithm:

1. parse -min_disabled_threshold arg (if not specified, will use default behavior)
2. for a group of clock nets, we calculate the TOTAL SUM of (1-D), aka, the total sum of how much a group of DFFEs is off!
3. if this number exceeds the argument for -min_disabled_threshold, we will create an ICG
4. We create the ICG and derive the GCLK activity/duty cycle from the EN and CLK products
5. Populate all cell attributes, we also limit the created ICG to a fanout of 1 for simplicity
6. The dffes converted to dffs will have their activities re-annotated, removing the EN and re-annotating the CLK value based on the same calculation mentioned above

[linear]

ENG-1992

[greptile-apps]

Greptile Summary

This PR adds an activity-based clock gating mode to the clockgate pass, controlled by a new -min_disabled_threshold argument. FFs are grouped by clock net, their cumulative disabled fraction is summed across all DFFEs, and clock gating is applied only when the sum exceeds the threshold; converted FFs and the new ICG also receive updated activity and duty-cycle annotations.

• Two new static helpers tokenize and rewrite space-separated activity attribute strings; both lack doc comments explaining input format and polarity-dependent default-value logic.
• The gated-clock activity value gclk_ackt is computed by multiplying two toggle rates together rather than scaling clock activity by the CE duty-cycle fraction, producing wrong activity annotations on every converted FF.
• A SigMap object is constructed inside the module loop but never applied to any signal, leaving it as dead code.

Confidence Score: 3/5

The circuit transformation is functionally correct, but the activity annotations written to every converted FF and the ICG cell use an incorrect formula, meaning downstream power analysis will produce wrong results.

The gclk_ackt value written to activity attributes on every gated FF multiplies two toggle rates together instead of scaling clock activity by the CE duty fraction, analogous to how gclk_duty is correctly computed. This silently produces wrong power estimates for every FF clock-gated by the new path. An unused SigMap and a helper that silently skips CLK updates when the token is absent add further uncertainty.

passes/techmap/clockgate.cc — specifically the gclk_ackt formula around line 476 and the update_ff_activity_attr helper at lines 206-217.

Important Files Changed

Filename	Overview
passes/techmap/clockgate.cc	Adds activity-based clock gating via -min_disabled_threshold; contains a likely incorrect gclk_ackt formula, an unused SigMap, and a helper that silently skips updating CLK when the token is absent.

Flowchart

%%{init: {'theme': 'neutral'}}%%
flowchart TD
    A[Parse -min_disabled_threshold arg] --> B{use_disabled_threshold?}
    B -- No --> C[Group FFs by clock net
qualify if net_size >= min_net_size]
    B -- Yes --> D[For each DFFE on clock net:
read EN duty cycle
compute disabled_frac = 1 - ce_active_frac
add to en_disabled_sum]
    D --> E{en_disabled_sum >= threshold?}
    E -- No --> F[Skip clock net]
    E -- Yes --> G[Create ICG cell
set CLK and CE ports]
    C --> G
    G --> H[Compute gclk_duty = clk_duty x ce_active_frac
gclk_ackt = clk_activity x ce_activity
Set ICG FANOUT=1 and activity attrs]
    H --> I[Connect ICG gated clock output wire]
    I --> J[For each DFFE in net:
Remove CE, repoint CLK to gated wire
Emit new DFF, update activity attrs]
    J --> K[Log converted FF count]

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_{Reviews (1): Last reviewed commit: "bug fixes" | Re-trigger Greptile}