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DMASpeed and DMAWidth doesn't limit SSD performance. #25

Description

@zinechant

Describe the bug

It seems that DMASpeed and DMAWidth don't limit SSD bandwidth.

To Reproduce

Steps to reproduce the behavior:
Modify sample.cfg in SimpleSSD-Standalone to avoid OS I/O stack being the bottleneck.

-blocksize = 4K
+blocksize = 128K

Modify sample.cfg in simplessd to avoid SSD DRAM being the bottleneck:

 ## DRAM structure parameters
-Channel = 1
+Channel = 4
Rank = 1
Bank = 8
Chip = 1

Please notice that this is SSD DRAM #channels, not SSD flash #channels.

Expected behavior

The performance should be limited by NVDDR transfers which is
DMASpeed * DMAWidth / 8 * #channels_in_SSD = 0.4 G/s * 1B * 8 = 3.2 GB/s
But the simulation results suggest the achieved SSD throughput is 11.14 GB/s.

I suspect it is related to how conflicts are resolved in PAL2.cc.
But I couldn't fully grasp the logic there.

Activity

  1. kukdh1 commented on Jul 15, 2022

    @kukdh1
    Collaborator

    Hi,

    I assume you only modified sample.cfg you mentioned.
    Please modify the following:

    • Change [global]Interface other than 0. If 0 (No interface) is selected, the latency model for host communication is not applied.
    • Change [generator]readwrite to randread or randwrite. Or, you can disable read prefetch from SSD configuration.

    Please let me know if your problem still exists.

    Thanks.

  2. zinechant commented on Jul 18, 2022

    @zinechant
    Author

    First, this DMASpeed, as I understand, is NVDDR DMA from flashes to SSD DRAM, not DMA from SSD to host DRAM. It is the NVDDR channel speed and width.
    Everything that references DMASpeed/NAND_DMA_SPEED/SPDIV is in PAL2.cc.
    Does [global]Interface really matter?

    Second, I changed [global]Interface to 1 (NVMe), and to [generator]randread. The performance is ~ 3.4 GB/s. But this doesn't change when I vary DMASpeed (e.g. lowering to 200 MB/s should lower the total throughput to 1.6GB/s, but the simulation result remains 3.4 GB/s).

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