3DIC timing analysis support in dbSta (Stages 0–8) by dsengupta0628 · Pull Request #10417 · The-OpenROAD-Project/OpenROAD

dsengupta0628 · 2026-05-13T14:44:32Z

Summary

Enable cross-chiplet STA on 3DBlox designs. read_3dbx now produces a single unified STA graph spanning multiple chiplets connected via bump pads / top-level nets / 3D bond regions. report_checks reports constrained flop-to-flop setup checks across chiplet boundaries with the natural create_clock [get_pins -of_objects [get_nets <top_net>]] SDC form. This version uses a zero-delay parasitic model on every chip-bump and chipnet — STA's fat-net wire-edge model traverses cross-chiplet connections directly. Per-dbChipConn RC binding (real bond/TSV delay) is deferred post-v1; the binding hook is Parasitics::makeParasiticNetwork(chipNet) when added.

Implemented in three commits:

Stages 0–6.5 — adapter foundation. Multi-block ownership in dbNetwork, pointer-tag encoding for dbChipBumpInst / dbChipInst / dbChipNet, chip-aware overrides in the four core iterators (childIterator, pinIterator, netIterator, NetPinIterator), term(Pin*) cross-boundary bridge, dbChipBumpInst 8-byte alignment fix, side-map for chip-bump VertexId, per-master synthetic Cell so cell(chip_inst) returns non-null, findInstance path-split for chipA/ff/CK-style queries.

Stage 7 — close cross-chiplet flop-to-flop path. direction(chip_bump) = BIDIRECT (Graph builds dual vertices + wire edges runs on every bump regardless of underlying bterm IoType). visitConnectedPins(Net*) chip-net branch descends each bump's inner net via term() so the fat-net wire-edge model reaches leaf loads across the boundary. Plus chip-bump clock-anchor caveat: synthetic LibertyCell per chiplet definition carries a zero-delay combinational self-arc per chip-bump port so Graph::makeInstanceEdges builds the internal load → bidir_drvr edge clock arrival needs; per-block 4-bit discriminator in getDbNwkObjectId so cross-block iterm/bterm/net ids don't collide in NetSet/PinSet.

Stage 8 — diagnostics. STA-3000 INFO summary on read_3dbx, STA-3001/3002 WARNs for orphan nets / unmapped bumps, Tcl helper report_3dic_summary. Fixture cleanup in 3dic_cross.tcl to satisfy upstream 3DBlox checker (Connection: + ground via bot: ~ + bmap XYs sized for BUMP macro center offset).

Tests: dbSta/test/3dic_cross.tcl (cross-chiplet flop-to-flop setup check, slack MET against 1 ns clock), dbSta/test/3dic_get_cells.tcl (structural iteration APIs). No src/sta/ edits.

Documentation: docs/contrib/3DIC.md.

Type of Change

New feature
Documentation update

Impact

Enable 3DIC timing analysis

Verification

I have verified that the local build succeeds (./etc/Build.sh).
I have run the relevant tests and they pass.
My code follows the repository's formatting guidelines.
I have included tests to prevent regressions.
I have signed my commits (DCO).

Related Issues

[Link issues here]

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions

Welcome to OpenROAD! Thanks for opening your first PR.
Before we review:

Contribution Guide: https://openroad.readthedocs.io/en/latest/contrib/contributing.html
Build Instructions: https://openroad.readthedocs.io/en/latest/contrib/BuildWithCMake.html

Please ensure:

CI passes
Code is properly formatted
Tests are included where applicable
A maintainer will review shortly!

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

gemini-code-assist

Code Review

This pull request enables 3DIC Static Timing Analysis (STA) by extending dbNetwork to support chiplet instances, chip-nets, and bump-inst pins, including ID disambiguation via block discriminators and synthesized LibertyCells for clock propagation. It also introduces 3DIC-aware iterators, diagnostic reporting, and comprehensive documentation, while ensuring proper object alignment for pointer tagging. Review feedback correctly identified an inconsistency in the documentation and warning messages regarding the .bmap file format, noting that bterm_name is the 5th column rather than the 4th.

gemini-code-assist · 2026-05-13T14:49:58Z

+1. **`.bmap` 4th column binds bump → chiplet port.**
+   Format per line: `<bump_inst_name> <BUMP_macro> <x> <y> <bterm_name> <signal>`.
+   `bterm_name = "-"` leaves the bump unbound — STA cannot cross that
+   boundary. Always set the 4th column to a real chiplet `dbBTerm` name
+   unless the test specifically exercises unmapped bumps.


The documentation regarding the .bmap file format is inconsistent. The format string on line 427 shows <bterm_name> as the 5th field, but the description on lines 426 and 429 refers to it as the "4th column". This is confusing for users trying to create these files.

To ensure clarity, please update the column number to be consistent with the format string. It should be the 5th column.

Additionally, the related warning message STA-3002 also mentions "col 4", which should probably be updated as well for consistency.

gemini-code-assist · 2026-05-13T14:49:58Z

+      logger_->warn(utl::STA,
+                    3002,
+                    "3DIC chiplet '{}': {}/{} bump pads not mapped to "
+                    "a chiplet port (missing name in .bmap col 4). "


The column number in this warning message appears to be incorrect. The .bmap format is <bump_inst_name> <BUMP_macro> <bterm_name> , which makes the bterm_name the 5th column, not the 4th. This inconsistency can be confusing for users.

Please update the column number in the message to 5 for accuracy.

Suggested change

"a chiplet port (missing name in .bmap col 4). "

"a chiplet port (missing name in .bmap col 5). "

github-actions

clang-tidy made some suggestions

github-actions · 2026-05-13T14:51:06Z

+  // Per-block discriminator stamped into upper bits of getDbNwkObjectId
+  // so iterms/bterms/insts/nets from different chiplet blocks (each
+  // numbered from 1) don't collide in NetSet/PinSet keys.
+  std::map<odb::dbBlock*, uint32_t> block_disc_;


warning: no header providing "uint32_t" is directly included [misc-include-cleaner]

src/dbSta/include/db_sta/dbNetwork.hh:5:

- #include <map> + #include <cstdint> + #include <map>

github-actions · 2026-05-13T14:51:06Z

+  LibertyBuilder builder(debug_, report_);
+  for (dbChipInst* chip_inst : chip->getChipInsts()) {
+    dbChip* master = chip_inst->getMasterChip();
+    if (master == nullptr || chip_master_cells_.count(master)) {


warning: use 'contains' to check for membership [readability-container-contains]

Suggested change

if (master == nullptr || chip_master_cells_.count(master)) {

;contains

github-actions · 2026-05-13T14:51:06Z

+
+  Pin* pin = db_network_->dbToSta(fake_bump);
+  ASSERT_NE(pin, nullptr);
+  EXPECT_EQ(reinterpret_cast<std::uintptr_t>(pin) & 0b111U, 4U);


warning: no header providing "std::uintptr_t" is directly included [misc-include-cleaner]

src/dbSta/test/cpp/TestDbSta.cc:4:

- #include <cstdio> + #include <cstdint> + #include <cstdio>

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions · 2026-05-13T15:54:11Z

clang-tidy review says "All clean, LGTM! 👍"

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions

clang-tidy made some suggestions

github-actions · 2026-05-13T16:55:53Z

 #include "dbChipBumpInst.h"

+#include <cstdint>
+


warning: included header cstdint is not used directly [misc-include-cleaner]

Suggested change

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

…nc is used Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions · 2026-05-13T18:10:53Z

clang-tidy review says "All clean, LGTM! 👍"

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions · 2026-05-13T19:10:42Z

clang-tidy review says "All clean, LGTM! 👍"

github-actions · 2026-05-13T19:17:57Z

clang-tidy review says "All clean, LGTM! 👍"

… the umbrella and migrated downstream BUILDs in the same commit Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

dsengupta0628 · 2026-05-13T19:36:28Z

https://docs.google.com/presentation/d/1uK_z-MXmKrwd2Y7NsbG-Ozl5qsI8Nqgf/edit?usp=drive_link&ouid=112535027494755707400&rtpof=true&sd=true is the presentation of the implementation

github-actions · 2026-05-13T19:41:11Z

clang-tidy review says "All clean, LGTM! 👍"

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions · 2026-05-13T20:16:05Z

clang-tidy review says "All clean, LGTM! 👍"

dsengupta0628 · 2026-05-13T20:44:36Z

https://jenkins.openroad.tools/job/OpenROAD-flow-scripts-Private/job/secure-3dic_sta/1/stages/

secure ci: http://secure-ci:8080/job/SB/job/secure-3dic_sta/

dsengupta0628 · 2026-05-13T20:47:08Z

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chatgpt-codex-connector · 2026-05-13T20:54:06Z

+  if (!bump_to_chip_net_.empty()) {
+    return;


Rebuild bump-net cache after chip-net edits

If client Tcl/C++ code creates or rewires a dbChipNet after this cache has already been populated (for example, querying timing/pins once and then adding a synthetic cross-chiplet net as the new tests do before any lookup), this early return keeps the stale map and dbNetwork::net(chip_bump_pin) returns null for the new connection, so STA silently misses the cross-chiplet path. Either invalidate on chip-net/bump edits or refresh entries even when the cache is non-empty.

Useful? React with 👍 / 👎.

Updated to refresh the cache when the net cache size changes

chatgpt-codex-connector · 2026-05-13T20:54:06Z

+  if (it == block_disc_.end()) {
+    return 0;
+  }
+  return (it->second & kBlockTagMask) << kBlockTagShift;


Guard against block discriminator wraparound

For 3DIC designs with 17 or more unique chiplet master blocks, the discriminator assigned in setTopChip() wraps through this 4-bit mask, so the 17th block reuses the first block's high bits and same-type db objects with the same local ODB id collide in STA PinSet/NetSet keys. Please reject oversized designs or allocate a non-wrapping id space; otherwise timing traversal can silently merge pins/nets across chiplets.

Useful? React with 👍 / 👎.

Upgraded to handle max 255 chiplets instead of 16. Also added an error message if it ixceeds

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions

clang-tidy made some suggestions

github-actions · 2026-05-13T22:46:02Z

+  // Caveat: in-place addBumpInst/removeBumpInst on an existing chip-net
+  // (no count change) is NOT detected — see 3DIC_TODO.md TODO 4.
+  mutable std::map<odb::dbChipBumpInst*, odb::dbChipNet*> bump_to_chip_net_;
+  mutable size_t bump_to_chip_net_cache_size_ = 0;


warning: no header providing "size_t" is directly included [misc-include-cleaner]

src/dbSta/include/db_sta/dbNetwork.hh:5:

- #include <cstdint> + #include <cstddef> + #include <cstdint>

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

github-actions · 2026-05-13T23:33:02Z

clang-tidy review says "All clean, LGTM! 👍"

dsengupta0628 added 7 commits May 12, 2026 19:18

changes till stage 6.5

9d38d7f

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stage 7 changes with caveat

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remove temp file

053b03d

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fix stage 7 caveat- works for clock at top clk nets too

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merged with latest master

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updated readme doc

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Stage 8 changes with reporting, diagnostic msgs, test amp

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dsengupta0628 self-assigned this May 13, 2026

clang formatted

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address clang review

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address some gemini and clang

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updated odb schema, address gemini and clang comments

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fix macOS build

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codegen to avoid adding include to both .h and .cpp when no getter fu…

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update docs, revert bazel gymnastics- fix probably needed in sta

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Merge branch 'master' into 3dic-sta-v1

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dsengupta0628 mentioned this pull request May 13, 2026

expose libertybuilder for 3DIC support in dbsta The-OpenROAD-Project/OpenSTA#362

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update sta build to expose libertybuilder for bazel

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visibility for dbsta/test, codex review address

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	"a chiplet port (missing name in .bmap col 4). "
	"a chiplet port (missing name in .bmap col 5). "

	if (master == nullptr \|\| chip_master_cells_.count(master)) {
	;contains

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dsengupta0628 commented May 13, 2026

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Impact

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Related Issues

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