Skip to content
View UmerShahidengr's full-sized avatar
13 followers · 17 following
  • RISC-V International
  • Lahore
  • 19:55 (UTC +05:00)

Achievements

Achievement: YOLOAchievement: Pull Sharkx2Achievement: Pair ExtraordinaireAchievement: Quickdraw

Achievements

Achievement: YOLOAchievement: Pull Sharkx2Achievement: Pair ExtraordinaireAchievement: Quickdraw

Organizations

@meds-ee-uet

Block or report UmerShahidengr

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
UmerShahidengr/README.md

Typing SVG


GitHub followers GitHub stars Profile Views RISC-V Member

🧬 About Me

name       : Umer Shahid
role       : Senior Engineer @ RISC-V International
location   : Lahore, Pakistan 🇵🇰  (UTC +05:00)

current_focus:
  - RISC-V Certification Program
  - RISC-V ISA Specification & Compliance
  - Architectural Certification Testing (riscv-arch-test / ACT)

expertise:
  - RISC-V Privileged & Unprivileged ISA
  - Architectural Compliance & Certification
  - SystemVerilog RTL Design & Verification
  - Embedded Systems & SoC Design

open_to    : ISA research, compliance tooling, open hardware projects

🔬 Open Source Contributions @ RISC-V International

Repository Org Description Role
🧪 riscv-arch-test riscv Architectural Certification Test suite for RISC-V implementations Contributor
📖 riscv-isa-manual riscv The official RISC-V Unprivileged & Privileged ISA Specification Contributor
⛵ sail-riscv riscv Formal Sail model of the RISC-V ISA — used as reference for compliance Contributor
🚀 riscv-isa-sim Fork Spike — the RISC-V ISA Reference Simulator Active Fork

💡 Most of my current work lives in upstream RISC-V International repositories rather than personal forks. Contributions include ISA spec edits, compliance test development, and formal model issues & PRs.

🛠️ Tech Stack

ISA & Formal Methods

RISC-V AsciiDoc LaTeX

Hardware & HDL

SystemVerilog Verilog

Software & Scripting

C C++ Python Bash

Tooling & Simulation

Spike Mentor Questa Xilinx Vivado Linux

📊 GitHub Statistics

GitHub Streak

📈 Contribution Activity

Activity Graph

🌐 Connect

LinkedIn Email GitHub

"An open ISA is the foundation of an open future."

Pinned Loading

  1. riscv-arch-test riscv-arch-test Public

    Forked from riscv/riscv-arch-test

    Assembly

  2. whisper whisper Public

    Forked from tenstorrent/whisper

    C++

  3. riscv/riscv-arch-test riscv/riscv-arch-test Public

    The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.

    Assembly 723 322

  4. riscv-software-src/riscof riscv-software-src/riscof Public archive

    Python 105 54

  5. ee-uet/UETRV-PCore ee-uet/UETRV-PCore Public

    Linux Capable 32-bit RISC-V based SoC in System Verilog

    VHDL 59 20