veriLogic-HDL

This repository provides a comprehensive set of Verilog HDL implementations covering fundamental digital logic design.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
Basic Gates		Basic Gates
Combinational Logic		Combinational Logic
Finite State Machines/State Machines		Finite State Machines/State Machines
Sequential Logic		Sequential Logic
.gitattributes		.gitattributes
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md

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