This repository contains a Verilog HDL implementation of a Traffic Light Controller system, designed for synthesis on FPGA/CPLD hardware. The project utilizes a Finite State Machine (FSM) to manage timing and transitions for a standard road intersection.

Project Components The design is highly modular, with specific Verilog files handling different aspects of the hardware logic:

control.v: The core Finite State Machine (FSM) that manages the logic for Red, Yellow, and Green light transitions.

counter55.v & counter05.v: Timing modules that define the duration of the light cycles (e.g., 55 units for Green, 5 units for Yellow).

datamux.v: A multiplexer used to route the correct timing data to the output interface based on the current state.

dataconvert05.v: Logic to convert internal data into a format suitable for hardware displays (like 7-segment displays).

How it Works The system cycles through four primary states to ensure safe traffic flow:

NS_Green / EW_Red: Traffic flows North-South (55s).

NS_Yellow / EW_Red: Transition state for North-South (5s).

NS_Red / EW_Green: Traffic flows East-West (55s).

NS_Red / EW_Yellow: Transition state for East-West (5s).

Development Environment Language: Verilog HDL

Synthesis Tool: Intel/Altera Quartus II

Hardware Target: FPGA / CPLD

Repository Structure /*.v: Verilog source files for all modules.

/db: Quartus II database files for synthesis and hardware mapping.

*.asm / *.map: Compilation and assembly output files.