feat(lab3.5): release - #47
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jjsnam
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Jul 28, 2026
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- Add Lab 3.5 documentation covering Ascend 910B architecture (AIC/AIV separation, UB/MTE2/MTE3/V pipelines, TQue/PipeBarrier sync), Ascend C API overview (LocalTensor/TBuf/TQue/TPosition, DataCopy(Pad), Cast/Add/ Reduce), profiling workflow (msprof op + simulator), and step-by-step optimization guide (pipeline, UB reuse, tiling, copy efficiency, reduction/precision).
- Add lab3.5 student kit under src/lab3p5/: env.sh, checker (build/run/ test_op/case_specs/get_time), and three implementation paths (src/ascendc baseline, src/triton, src/tilelang).
- Ascend C baseline: row-parallel FP16 I/O with FP32 compute, DataCopyPad for non-aligned tail, BlockReduceSum + WholeReduceSum for the H-axis reduction, TQue double-buffered in/out queues.
- Document scoring curve (120-point scale, 20-point bonus) and submission rules (upload src// only).
- Add Lab 3.5 documentation covering Ascend 910B architecture (AIC/AIV separation, UB/MTE2/MTE3/V pipelines, TQue/PipeBarrier sync), Ascend C API overview (LocalTensor/TBuf/TQue/TPosition, DataCopy(Pad), Cast/Add/ Reduce), profiling workflow (msprof op + simulator), and step-by-step optimization guide (pipeline, UB reuse, tiling, copy efficiency, reduction/precision). - Add lab3.5 student kit under src/lab3p5/: env.sh, checker (build/run/ test_op/case_specs/get_time), and three implementation paths (src/ascendc baseline, src/triton, src/tilelang). - Ascend C baseline: row-parallel FP16 I/O with FP32 compute, DataCopyPad for non-aligned tail, BlockReduceSum + WholeReduceSum for the H-axis reduction, TQue double-buffered in/out queues. - Document scoring curve (120-point scale, 20-point bonus) and submission rules (upload src/<lang>/ only). Signed-off-by: jjsnam <jjsnam@zju.edu.cn> Co-Authored-By: Sushidesu486 <shouss@zju.edu.cn> Co-Authored-By: zgyxclyty <zh1553525690@outlook.com> Co-Authored-By: ckyasb <3376380559@qq.com> Co-Authored-By: Hzw-ZuttoZutto <692596316@qq.com>
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