ZiaCheemaGit · ZiaCheemaGit · Jun 21, 2026 · Jun 18, 2026 · Jun 18, 2026 · Jun 20, 2026
diff --git a/hardware/MMU/MMU.v b/hardware/MMU/MMU.v
@@ -48,7 +48,7 @@ module MMU(
     wire boot_rom_read = mem_read_cpu && is_boot_rom;
     assign ram_read = mem_read_cpu && is_ram;
     assign ram_write = mem_write_cpu && is_ram;
-    assign vram_read = mem_read_cpu && is_vram;
+    wire vram_read = mem_read_cpu && is_vram;
     assign vram_write = mem_write_cpu && is_vram;
 
     wire uart_tx_status_read = mem_read_cpu && is_uart_tx_status;

diff --git a/hardware/VGA/vram.v b/hardware/VGA/vram.v
@@ -7,8 +7,8 @@ module vram(
 
     input we_cpu,
     input [17:0] addr_cpu,
-    input [1:0] data_cpu,
-    output reg [1:0] data_cpu_out
+    input [1:0] data_cpu
+    //output reg [1:0] data_cpu_out
 );
 
 	reg [1:0] mem [0:153599];
@@ -20,7 +20,7 @@ module vram(
 		if (we_cpu)
 			mem[addr_cpu] <= data_cpu;
 
-		data_cpu_out <= mem[addr_cpu];
+		//data_cpu_out <= mem[addr_cpu];
 	end
 
 endmodule

diff --git a/hardware/memories/boot_rom.v b/hardware/memories/boot_rom.v
@@ -33,6 +33,7 @@ module boot_rom(
             $display("Loading program from: %s", program_file);
             $readmemh(program_file, mem);
         end
+    `elsif YOSYS
     `else
         initial begin
             $readmemh("D:/git-clones/pc-one/software/build/BIOS/bios.hex", mem);

diff --git a/hardware/pc_one/pc_one.v b/hardware/pc_one/pc_one.v
@@ -43,7 +43,7 @@ module pc_one(
         .mem_add_ram(mem_add_ram)
     );
 
-    five_stage_pipelined_rv32i_core core_instance(
+    single_cycle_rv32i_core core_instance(
         .clk(clk_from_FPGA),
         .rst(rst_from_FPGA),
         .instruction_address(instr_add),
@@ -115,8 +115,8 @@ module pc_one(
         .data_vga(vga_data),
         .we_cpu(vram_write),         
         .addr_cpu(vram_add),       
-        .data_cpu(data_from_cpu[1:0]),        
-        .data_cpu_out()          
+        .data_cpu(data_from_cpu[1:0])       
+        //.data_cpu_out()          
     );
 
 endmodule

diff --git a/hardware/processors/single_cycle_rv32i_core/single_cycle_rv32i_core.v b/hardware/processors/single_cycle_rv32i_core/single_cycle_rv32i_core.v
@@ -56,7 +56,7 @@ module single_cycle_rv32i_core(
         .s_type_immediate(s_type_immediate)
     );
 
-    wire func3, reg_write_control;
+    wire func3, reg_write_control, unsigned_op;
     wire [1:0] alu_op_control, pc_src, alu_src_control;
     wire [2:0] mem_to_reg_control;
     control_unit control_unit_instance(

diff --git a/misc/hardware/MMU.png b/misc/hardware/MMU.png
diff --git a/misc/hardware/Makefile b/misc/hardware/Makefile
@@ -1,31 +1,42 @@
-all: MMU.png pc_one.png RAM.png ROM.png RV32I.png UART.png clean
+all: MMU.png pc_one.png RAM.png ROM.png RV32I_SINGLE_CYCLE.png UART.png RV32I_FIVE_STAGE_PIPELINED.png clean
 
 
 # Verilog to JSON
 
 MMU.json:
-	yosys -p "read_verilog ../hardware/MMU/*.v; hierarchy -top MMU; proc; opt; write_json MMU.json"
+	yosys -p "read_verilog ../../hardware/MMU/*.v; hierarchy -top MMU; proc; opt; write_json MMU.json"
 
 pc_one.json:
-	yosys -p "read_verilog \
-	../hardware/pc_one/pc_one.v \
-	../hardware/UART/*.v \
-	../hardware/single_cycle_rv32i_core/*.v \
-	../hardware/memory/ram.v \
-	../hardware/memory/rom.v \
-	../hardware/MMU/*.v; hierarchy -top pc_one; proc; opt; write_json pc_one.json"
+	yosys -p "read_verilog -lib ../../hardware/memories/ram.v ../../hardware/memories/boot_rom.v ../../hardware/VGA/vram.v; \
+	read_verilog \
+	../../hardware/pc_one/pc_one.v \
+	../../hardware/UART/*.v \
+	../../hardware/processors/single_cycle_rv32i_core/*.v \
+	../../hardware/processors/lib/*.v \
+	../../hardware/VGA/vga_controller.v \
+	../../hardware/MMU/*.v; \
+	hierarchy -top pc_one; proc; opt; write_json -compat-int pc_one.json"
 
 RAM.json:
-	yosys -p "read_verilog ../hardware/memory/ram.v; hierarchy -top ram; proc; opt; write_json RAM.json"
+	yosys -p "read_verilog ../../hardware/memories/ram.v; hierarchy -top ram; proc; opt; write_json RAM.json"
 
 ROM.json:
-	yosys -p "read_verilog ../hardware/memory/rom.v; hierarchy -top rom; proc; opt; write_json ROM.json"
+	yosys -p "read_verilog ../../hardware/memories/boot_rom.v; hierarchy -top boot_rom; proc; opt; write_json ROM.json"
+
+RV32I_SINGLE_CYCLE.json:
+	yosys -p "read_verilog \
+	../../hardware/processors/single_cycle_rv32i_core/*.v \
+	../../hardware/processors/lib/*.v; \
+	hierarchy -top single_cycle_rv32i_core; proc; opt; write_json RV32I_SINGLE_CYCLE.json"
 
-RV32I.json:
-	yosys -p "read_verilog ../hardware/single_cycle_rv32i_core/*.v; hierarchy -top core; proc; opt; write_json RV32I.json"
+RV32I_FIVE_STAGE_PIPELINED.json:
+	yosys -p "read_verilog \
+	../../hardware/processors/five_stage_pipelined_rv32i_core/*.v \
+	../../hardware/processors/lib/*.v; \
+	hierarchy -top five_stage_pipelined_rv32i_core; proc; opt; write_json RV32I_FIVE_STAGE_PIPELINED.json"
 
 UART.json:
-	yosys -p "read_verilog ../hardware/UART/*.v; hierarchy -top uart_tx; proc; opt; write_json UART.json"
+	yosys -p "read_verilog ../../hardware/UART/*.v; hierarchy -top uart_tx; proc; opt; write_json UART.json"
 
 
 # JSON to SVG
@@ -42,8 +53,11 @@ RAM.svg: RAM.json
 ROM.svg: ROM.json
 	netlistsvg ROM.json -o ROM.svg
 
-RV32I.svg: RV32I.json
-	netlistsvg RV32I.json -o RV32I.svg
+RV32I_SINGLE_CYCLE.svg: RV32I_SINGLE_CYCLE.json
+	netlistsvg RV32I_SINGLE_CYCLE.json -o RV32I_SINGLE_CYCLE.svg
+
+RV32I_FIVE_STAGE_PIPELINED.svg: RV32I_FIVE_STAGE_PIPELINED.json
+	netlistsvg RV32I_FIVE_STAGE_PIPELINED.json -o RV32I_FIVE_STAGE_PIPELINED.svg
 
 UART.svg: UART.json
 	netlistsvg UART.json -o UART.svg
@@ -63,17 +77,20 @@ RAM.png: RAM.svg
 ROM.png: ROM.svg
 	rsvg-convert -b white ROM.svg -o ROM.png
 
-RV32I.png: RV32I.svg
-	rsvg-convert -b white RV32I.svg -o RV32I.png
+RV32I_SINGLE_CYCLE.png: RV32I_SINGLE_CYCLE.svg
+	rsvg-convert -b white RV32I_SINGLE_CYCLE.svg -o RV32I_SINGLE_CYCLE.png
+
+RV32I_FIVE_STAGE_PIPELINED.png: RV32I_FIVE_STAGE_PIPELINED.svg
+	rsvg-convert -b white RV32I_FIVE_STAGE_PIPELINED.svg -o RV32I_FIVE_STAGE_PIPELINED.png
 
 UART.png: UART.svg
 	rsvg-convert -b white UART.svg -o UART.png
 
 
 # clean
 
+clean_all:
+	rm -f *.json *.svg *.png
+
 clean:
 	rm -f *.json *.svg
-
-clean_png:
-	rm -f *.png
diff --git a/misc/hardware/RAM.png b/misc/hardware/RAM.png
diff --git a/misc/hardware/ROM.png b/misc/hardware/ROM.png
diff --git a/misc/hardware/RV32I_FIVE_STAGE_PIPELINED.png b/misc/hardware/RV32I_FIVE_STAGE_PIPELINED.png
diff --git a/misc/hardware/RV32I_SINGLE_CYCLE.png b/misc/hardware/RV32I_SINGLE_CYCLE.png
diff --git a/misc/hardware/UART.png b/misc/hardware/UART.png
diff --git a/misc/hardware/pc_one.png b/misc/hardware/pc_one.png
diff --git a/tests/hardware/FPGA/Makefile b/tests/hardware/FPGA/Makefile
@@ -1,13 +1,14 @@
 # Makefile
-
+PWD := $(shell pwd)
 # simulator
 SIM ?= icarus
 
 # hdl 
 TOPLEVEL_LANG ?= verilog
 
-# Processor to use: five_stage_pipelined_rv32i_core files
+# Processors options
 VERILOG_SOURCES += $(PWD)/../../../hardware/processors/five_stage_pipelined_rv32i_core/five_stage_pipelined_rv32i_core.v
+VERILOG_SOURCES += $(PWD)/../../../hardware/processors/single_cycle_rv32i_core/single_cycle_rv32i_core.v
 
 # Processor Lib files
 VERILOG_SOURCES += $(PWD)/../../../hardware/processors/lib/*.v

diff --git a/tests/hardware/pc_one/test.py b/tests/hardware/pc_one/test.py
@@ -69,6 +69,11 @@ async def test_basic_asm(dut):
         if dut.boot_rom_instance.pc.value.to_unsigned() == 0x130:
             logger.critical("Test ended control reached at label HALT")
             await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
 
             result = dut.core_instance.reg_file_instance.registers[1]
             try:
@@ -120,6 +125,11 @@ async def test_load_asm(dut):
         if dut.boot_rom_instance.pc.value.to_unsigned() == 0x88:
             await RisingEdge(dut.clk_from_FPGA)
             await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+
             logger.critical("Test Ended")
             test_ended = True
 
@@ -175,6 +185,11 @@ async def test_load_neg_asm(dut):
         if dut.boot_rom_instance.pc.value.to_unsigned() == 0xa8:
             await RisingEdge(dut.clk_from_FPGA)
             await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+
             logger.critical("Test Ended")
             test_ended = True
 
@@ -223,6 +238,14 @@ async def test_math_c(dut):
         address = 0x0
 
         if dut.boot_rom_instance.pc.value.to_unsigned() == 0x58:
+
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+
             logger.critical("Test ended PC reached 0x58")
             word_index = address >> 2
             result = dut.ram_instance.mem[word_index].value.to_unsigned()
@@ -274,6 +297,25 @@ async def test_aggressive_c(dut):
         address = 0x0
 
         if dut.boot_rom_instance.pc.value.to_unsigned() == 0x58:
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+            await RisingEdge(dut.clk_from_FPGA)
+
             logger.critical("Test ended PC reached 0x58")
             result = dut.ram_instance.mem[address].value.to_unsigned()
 

diff --git a/tests/hardware/processors/single_cycle_rv32i_core/Makefile b/tests/hardware/processors/single_cycle_rv32i_core/Makefile
@@ -1,26 +1,21 @@
 # Makefile
-
+PWD := $(shell pwd)
 # simulator
 SIM ?= icarus
 
 # hdl 
 TOPLEVEL_LANG ?= verilog
 
 # single_cycle_rv32i_core files
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/single_cycle_rv32i_core.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/adder32.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/alu_control.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/control_unit.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/main_alu.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/mux_4X1.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/mux_5X1.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/pc.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/pc_src_control.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/register_file.v
-VERILOG_SOURCES += $(PWD)/../../../hardware/single_cycle_rv32i_core/sign_ext_12_to_32.v
+VERILOG_SOURCES += $(PWD)/../../../../hardware/processors/five_stage_pipelined_rv32i_core/five_stage_pipelined_rv32i_core.v
+
+VERILOG_SOURCES += $(PWD)/../../../../hardware/processors/single_cycle_rv32i_core/single_cycle_rv32i_core.v
+
+# processor lib files
+VERILOG_SOURCES += $(PWD)/../../../../hardware/processors/lib/*.v
 
 # COCOTB_TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
-COCOTB_TOPLEVEL = core
+COCOTB_TOPLEVEL = five_stage_pipelined_rv32i_core
 
 # COCOTB_TEST_MODULES is the basename of the Python test file(s)
 COCOTB_TEST_MODULES = test_core