SystemVerilog GameBoy CPU

Description

This project aims to build a GameBoy CPU with the following functionality:

• Execute GameBoy opcodes with complete Cycle-Accuracy
• Implement the Timer Circuit
• Service Timing Interups
• Handle the Halt Bug (should work, can't confirm until PPU is added)
  • ei before halt, (IE&IF != 0, IME = 0), call ISR but return to halt
  • rst after halt bug (IE&IF != 0, IME = 0), push address of rst to stack, not rst+1
  • halt, (IE&IF != 0, IME = 0), read next opcode twice
  • halt, (IE&IF != 0, IME = 1), call ISR and continue normally
  • ei before halt, (IE&IF != 0, IME = 0), rst after halt. Call ISR, return to halt, rst works normally

The following components are not in the scope of this repository:

• PPU
• APU
• DMA
• Boot ROM
• MBC Cartridges

Test Status

blargg

Test	Result
cpu_instrs	✅
instr_timing	✅
mem_timing	✅
halt_bug	❌ (requires Vblank interrupt, can't test in this scope)

Resources

Name	Description
GameBoy Instruction Set	Table View of GameBoy Opcodes
PanDocs	General Device Documentation
rgbds Docs	In-Depth Command Documentation
GameBoy Complete Technical Reference	Cycle-by-Cycle Opcode Breakdowns
mGBA gbdoc	Additional Device Documentation
blarggs Test ROMS	Test ROMS
Mooneye Test ROMS	Test ROMS
GameBoy Doctor	Support Tool for blargg Test ROMS