Asynchronous_FIFO

An asynchronous fifo keeps two independent clocks: one for writing (wt_clk) and one for reading (rd_clk). It can safely pass the data between different clock speeds and phases. This is called as Clock Domain Crossing.

Differences from a standard Synchronous Fifo:

• Dual-Clock Memory Array: It has separate clocks - wt_clk (for write operation) and rd_clk (for read operation), which are generally out of phase or frequency.
• Gray Code Pointers: Standard binary pointers are not suitable because many bits changing at once can cause errors. They must be converted to Gray code so that only one bit changes at a time.
• 2-stage Flip-Flop synchronizer: It pulls the read-pointer into the write domain,, and write-pointer in the read domain.
• Flag Logic:
  • The full flag is calculated in the write clock domain.
  • The empty flag is calculated in the read clock domain.
  • (Due to synchronization delays, flags might report full/empty slightly longer than expectation, but this prevents data loss.)