Popular repositories Loading
-
FPGA-based-RISC-V-Processor-Customizable-for-AI-Applications
FPGA-based-RISC-V-Processor-Customizable-for-AI-Applications PublicFPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Full…
Verilog 3
-
ML-based-heart-rate-anomaly-detector-for-RISC-V
ML-based-heart-rate-anomaly-detector-for-RISC-V PublicLightweight, low-power heart-rate anomaly detector for wearable devices. Implements a fixed-point linear regression model on a custom RV32I processor, fully FPGA-compatible with BRAM memory support…
Python 1
-
Hardware-Accelerated-Heart-Rate-Anomaly-Detection
Hardware-Accelerated-Heart-Rate-Anomaly-Detection PublicRTL implementation of a RISC-V processor integrated with a custom hardware accelerator for heart-rate anomaly detection. The SoC-style architecture uses memory-mapped I/O to transfer physiological …
Verilog 1
-
-
-
If the problem persists, check the GitHub status page or contact support.