fix(vllm): prevent Ultra DS-tail copy offset overflow

[sungsooha]

Overview:

Fix a Nemotron Ultra DS-layout Mamba conv-state tail-copy overflow that can surface as CUDA illegal memory access under GB200 long-context MTP traffic.

The failing path is specific to prefix cache ON + VLLM_SSM_CONV_STATE_LAYOUT=DS + --mamba-cache-mode align + MTP. The DS-tail Triton copy kernel can compute source/destination element offsets above signed 32-bit range; this PR keeps that pointer-offset arithmetic in tl.int64.

Details:

• Adds 0005-ultra-ds-tail-copy-i64-offsets.patch.
• Updates ds_conv_tail_copy_kernel so rows/cols and block/stride/offset operands are converted to tl.int64 before pointer-offset multiplication/addition.
• Preserves existing copy semantics, masks, source/destination block ids, and load/store shape.
• Adds runtime validation marker NEMOTRON_ULTRA_DS_TAIL_I64_OFFSET_FIX under the existing mtp_ds_copy marker group.

Validation evidence:

• Original prod DS-tail kernel reproduced the hard stop with valid DS-tail copies and destination offsets above 2^31:
  • dst_over2G_count=37
  • max_dst_elem_offset=2679660544
  • direct hard stop in ds_conv_tail_copy_kernel
• i64 candidate completed the same risky GB200 c16 sticky long-context condition cleanly:
  • ds_tail_count=128
  • dst_over2G_count=48
  • max_dst_elem_offset=2840651774
  • hard stops: 0

Where should the reviewer start?

• container/deps/vllm/patches/v0.22.0/ultra/0005-ultra-ds-tail-copy-i64-offsets.patch
• container/deps/vllm/validate_nemotron_ultra_runtime.py

Related Issues

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🔗 This PR is linked to an issue:

• Closes #XXXX

🚫 This PR is NOT linked to an issue:

• Confirmed — no related issue

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