This repository hosts the development of a sigma-delta digital-to-analog converter (DAC) implementation on FPGA.
The S-D DACs uses less analog circuitry at the expense of more digital circuitry compared to the Nyquist rate DACs. This is done using the concepts of oversampling and noise shaping. The figure below shows a block diagram of a S-D DAC. The digital parts of the S- D DAC are the IF and the digital S-D modulator, while the analog parts are the M -bit internal DAC, and the analog LPF.
The IF is an essential part of the S-D DAC and can have a big impact on the overall power consumption and performance of the DAC. The cascaded integrator-comb (CIC) filter is a subclass of linear phase FIR filters for decimation and interpolation, which uses no multiplication and limited storage. Figure below shows the basic structure of the CIC IF.
The delta sigma modulator is the core of delta sigma converters. The average level of the produced bitstream represents the input signal level. A simple digital first order delta sigma modulator block diagram looks like this:
The bitstream signal can be viewed as having its information predominantly situated within the lower frequency band, while containing substantial noise in higher frequencies. The low pass filter at the output is needed to average out the signal of the bitstream.
Digital data can be efficiently converted into analog format using FPGA, enabling a wide range of applications in electronics, communications, medicine, and other industries. With the implementation of Sigma-Delta converters, high precision and efficiency in conversion are achieved. FPGA technology further allows flexibility and adaptability in converter implementation, facilitating the integration of complex functionalities of digital-to-analog conversion. Research on this topic focuses on optimizing and adapting analog converter parameters using digital design and digital signal processing.