Status note: This repository is currently documentation of completed coursework, not a published source-code/schematic-file project. The original circuit designs were completed for a university digital electronics module (Hochschule Hannover) and the schematic files are not yet uploaded here. This README describes the project honestly based on the actual work completed.
Design, optimization, and testing of digital circuits combining combinational and sequential logic, including comparator circuits.
Deepen the fundamentals of digital circuit design along with systematic optimization and verification of logic circuits.
| Category | Tools |
|---|---|
| Logic Design | Truth tables, Karnaugh maps |
| Circuit Tools | Schematic design/simulation tools |
- Combinational and sequential logic
- Comparator circuits
- Logic minimization (Karnaugh maps)
- Circuit verification
- Formulate requirements as a truth table.
- Derive minimized logic expressions.
- Implement as a schematic.
- Functionally verify and test the circuit.
- Systematic logic minimization for more complex truth tables.
- Ensuring correct behavior of sequential elements across all input combinations.
- Digital circuit design
- Logic optimization
- Structured verification and test methodology
- Port the design to an FPGA implementation.
- Extend to more complex arithmetic or sequential building blocks.
MIT — see LICENSE.
Abdellatif Ali — B.Sc. Elektro- und Informationstechnik, Hochschule Hannover LinkedIn