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Test Bench Outputs

NOTE: For ADDR_ACK state there is an extra delay of one cycle usde for proper timing while for DATA_ACK no delay is used

1. Writing into Slave Case Writing into slave case

2. Reading from Slave Case Read from slave

3. Address Mismatch Case

NOTE: For this case slave address was set as 0x01 Wrong address case

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I2C Protocol implementation using Verilog

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