feat/cuda: I2 - tensor layer (device alloc, host<->device copies, file streaming) - #21
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magiodev wants to merge 7 commits into
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feat/cuda: I2 - tensor layer (device alloc, host<->device copies, file streaming)#21magiodev wants to merge 7 commits into
magiodev wants to merge 7 commits into
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…l, 100 op stubs) - Add h3_cuda.cu: implements the existing plain-C h3_gpu.h API against CUDA/cuBLAS. h3_cuda_probe + h3_gpu_create/free/error real; all compute ops are stubs returning 'not yet implemented'. Metal backend (h3_gpu.m/h3_shaders.metal) preserved untouched. - Add h3_cuda.h (probe decl); h3.c probes via H3_CUDA guard. - Add h3_tokenizer.c C stub (Linux has no Foundation; Metal keeps h3_tokenizer.m). - h3_host.c: vImage high-quality scale guarded, portable bilinear fallback for CUDA build. - h3.c/h3_cli.c/h3_ffmpeg.c: Linux portability guards (st_mtimespec->st_mtim, arc4random_buf->getrandom, SSIZE_MAX define). - Makefile: cuda-spark/cuda-generic/cuda targets (nvcc + cuBLAS, .cuda.o objects, CUDA_ARCH=sm_121 for DGX Spark GB10), mirroring ds4's pattern.
…CK_MONOTONIC/strdup)
…urns cast to exact type
…removed prop.unifiedMemory)
…h in h3_cuda.cu nvcc compiles .cu as C++; without C linkage the GPU API symbols were mangled and the host C objects could not link. extern "C" guards are compile-time only and inert for the Metal build (.c/.m never define __cplusplus).
… command-buffer no-ops, stats - h3_gpu_tensor_new/from_*: cudaMalloc + host->device copy (f32/bf16/i8/u32) - h3_gpu_tensor_load_bf16/f32 + read_file_bf16/stream_file_bf16: chunked pread -> host staging -> device (1MB chunks; no host double-buffer of big weights) - h3_gpu_tensor_read/write_*: device<->host cudaMemcpy with bounds checks - h3_gpu_begin/continue/submit: no-ops (CUDA has no explicit command buffer) - h3_gpu_get_stats: allocated/live/peak bytes + tensor_allocations tracking - tensor_free: cudaFree + stats decrement; tensor struct carries owner - capability flags (is_m5/has_int8_mlp/has_nax_mlp) still return 0 (no int8/nax fast paths yet)
This was referenced Aug 12, 2026
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Stacked PR 2/2, on top of #20 (I1 scaffold). Once #20 merges this diff narrows to I2 only.
I2 tensor layer, real in h3_cuda.cu:
Build-gated on DGX Spark: make cuda-spark clean.