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aolofsson / oh Public

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Spi cpol0 cpha0#85

Open

olajep wants to merge 18 commits intoaolofsson:mainaolofsson/oh:mainfrom

olajep:spi-cpol0-cpha0olajep/oh:spi-cpol0-cpha0Copy head branch name to clipboard

Conversation Commits18 (18)Checks Files changed

Open

Spi cpol0 cpha0#85
olajep wants to merge 18 commits intoaolofsson:mainfrom
olajep:spi-cpol0-cpha0

Commits

Commits on May 27, 2016

spi: Connect nreset of oh_rise2pulse
olajep
committed
spi: fpga: Add constraint for master slave clock out
olajep
committed
oh_fifo_async: Error on invalid TARGET/PARAMETERS
olajep
committed
spi: fpga: Add fifo_async_104x32 ip
olajep
committed
common: oh_par2ser: Reset shiftreg to zero on nreset
olajep
committed
common: oh_ser2par: Add dout_reg
olajep
committed
spi: spi_master_io: Sample MISO on rising edge of SCLK
olajep
committed
spi: spi_master_regs: Connect nreset to e2pulse
olajep
committed

Commits on May 29, 2016

spi: Rewrite slave to be CPOL=0 CPHA=0 compliant.
olajep
committed
[HACK] spi: spi_master_fifo: Use oh_fifo_cdc for XILINX
olajep
committed
spi: dv: Add 'high bits' test
olajep
committed
scripts: view.sh: Fix path to presets file
olajep
committed
spi: spi_slave_io: Add default case to state machine
olajep
committed
parallella: pgpio: Add parameter for SLEW rate
olajep
committed
spi: parallell_spi: Set gpio pin SLEW rate to "FAST"
olajep
committed
spi: fpga: Update timing constraints
olajep
committed
spi: parallella_spi: Fix pin directions
olajep
committed
spi: spi_master_io: Add 1 cycle grace period between transfers
olajep
committed

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