SoC Register Validation Framework

A modular and extensible Python-based automation framework for validating System-on-Chip (SoC) register maps. The framework verifies register functionality, access permissions, reset values, reserved bits, and bitfields while generating comprehensive validation reports in HTML, CSV, and JSON formats.

Overview

Modern SoCs contain hundreds or thousands of memory-mapped registers. Manually validating these registers is repetitive, error-prone, and difficult to maintain.

This framework automates the validation process by reading register definitions from CSV files, executing multiple validation checks through a modular validation engine, and generating detailed reports. The framework supports both a simulated memory model for development and a Memory-Mapped I/O (MMIO) interface for hardware integration.

Features

• Modular validation framework
• Register Reset Value Validation
• Read/Write Validation
• Access Permission Validation (RO, RW, WO, W1C)
• Reserved Bit Validation
• Bitfield Validation
• Simulated Memory Interface
• MMIO Hardware Interface
• Register Coverage Analysis
• HTML Report Generation
• CSV Report Generation
• JSON Summary Report
• YAML Configuration Support
• Command Line Interface (CLI)
• Logging Support
• Unit Testing with PyTest
• GitHub Actions Continuous Integration

Architecture

                    +----------------------+
                    |      app.py          |
                    +----------+-----------+
                               |
                     Command Line Arguments
                               |
                     Configuration Loader
                               |
            +------------------+------------------+
            |                                     |
     Register Parser                    Bitfield Parser
            |                                     |
            +------------------+------------------+
                               |
                      Validation Runner
                               |
      +-----------+------------+-------------+-----------+-----------+
      |           |            |             |           |           |
 Reset      Read/Write     Access      Reserved     Bitfield    Future
Validator    Validator     Validator   Validator    Validator   Modules
      |           |            |             |           |
      +-----------+------------+-------------+-----------+
                               |
                    Hardware Interface Layer
                               |
              +----------------+----------------+
              |                                 |
     Simulated Memory                  MMIO Interface
              |                                 |
              +----------------+----------------+
                               |
                      Validation Results
                               |
       +-----------------------+-----------------------+
       |                       |                       |
   HTML Report            CSV Report            JSON Summary

---

Project Structure

SoC_Register_Validation/
│
├── .github/
│   └── workflows/
│       └── python-tests.yml
│
├── config/
├── coverage/
├── engine/
├── hal/
├── logger/
├── models/
├── parser/
├── register_db/
├── report/
├── tests/
├── validation/
├── docs/
│   └── images/
│       └── html_report.png
│
├── output/
│
├── app.py
├── requirements.txt
├── README.md
├── LICENSE
└── .gitignore

---

Validation Modules

Reset Validator

Verifies that every register contains the expected reset value immediately after device reset.

Read/Write Validator

Ensures writable registers correctly store and return written values.

Access Validator

Checks register access permissions including:

• Read Only (RO)
• Read Write (RW)
• Write Only (WO)
• Write-One-to-Clear (W1C)

Reserved Bit Validator

Verifies that reserved bits remain unchanged after write operations.

Bitfield Validator

Validates register bitfields by checking field positions, widths, reset values, and access permissions.

---

Hardware Interfaces

Simulated Memory

A software-based register model used for development, testing, and continuous integration without requiring physical hardware.

MMIO Interface

A Memory-Mapped I/O interface designed for integration with real embedded hardware.

---

Reports

After validation, the framework automatically generates:

• HTML Validation Report
• CSV Validation Report
• JSON Summary Report

Output directory:

output/
├── report.html
├── report.csv
└── summary.json

---

HTML Validation Report

The framework generates a detailed HTML report that summarizes validation results, register information, pass/fail statistics, and coverage information.

---

Register Coverage

The framework provides register coverage statistics including:

• Total Registers
• RW Registers
• RO Registers
• WO Registers
• W1C Registers
• Overall Coverage Percentage

Example:

Total Registers : 30
RW Registers    : 16
RO Registers    : 9
WO Registers    : 3
W1C Registers   : 2
Coverage        : 100.00%

---

Installation

Clone the repository:

git clone https://github.com/<ashyadav108>/SoC_Register_Validation.git

cd SoC_Register_Validation

Install dependencies:

pip install -r requirements.txt

---

Running the Framework

Run all validators:

python app.py

Run Reset Validation:

python app.py --reset

Run Read/Write Validation:

python app.py --rw

Run Access Validation:

python app.py --access

Run Reserved Bit Validation:

python app.py --reserved

Run Bitfield Validation:

python app.py --bitfield

Run all validations explicitly:

python app.py --all

Use MMIO interface:

python app.py --interface mmio

Specify a custom register database:

python app.py --register-db register_db/registers.csv

Specify a custom output directory:

python app.py --output output

---

Sample Console Output

Validation Summary

Total Tests : 191
Passed      : 191
Failed      : 0

Coverage : 100%

---

Unit Testing

Run all unit tests:

python -m pytest

Verbose mode:

python -m pytest -v

Example output:

==========================
11 passed in 0.17s
==========================

---

Technologies Used

• Python 3.12
• PyTest
• Jinja2
• PyYAML
• HTML
• CSV
• JSON
• Git
• GitHub Actions

---

Future Improvements

• IP-XACT Register Parser
• Excel Register Database Support
• XML Register Database Parser
• UVM Register Model Integration
• Functional Coverage Dashboard
• PDF Report Generation
• Register Difference Tool
• Hardware Register Dump Comparison
• Jenkins CI/CD Integration
• REST API Support

---

License

This project is licensed under the MIT License.

---

Author

Developed as a modular SoC Register Validation Framework to demonstrate scalable software design, embedded systems verification, register validation automation, and modern Python engineering practices.