prove: arch::pci (x86) & io

README.md

@@ -5,7 +5,7 @@
 [![verify (verus-lang/verus)](https://img.shields.io/github/actions/workflow/status/asterinas/vostd/ci-upstream-verus.yml?branch=main&label=verify%20(verus-lang%2Fverus))](https://github.com/asterinas/vostd/actions/workflows/ci-upstream-verus.yml)
 
 > [!NOTE]
-> This repository is currently in a transitional state: the components under `ostd/src/sync` and `ostd/libs/id-alloc` already track the upcoming Asterinas release [v0.18.1](https://github.com/asterinas/asterinas/releases/tag/v0.18.1), while every other OSTD component is still based on [v0.16.0](https://github.com/asterinas/asterinas/releases/tag/v0.16.0).
+> This repository is currently in a transitional state: the components under `ostd/src/sync`, `ostd/libs/id-alloc` and `ostd/src/io/io_port` already track the upcoming Asterinas release [v0.18.1](https://github.com/asterinas/asterinas/releases/tag/v0.18.1), while every other OSTD component is still based on [v0.16.0](https://github.com/asterinas/asterinas/releases/tag/v0.16.0).
 
 ## Overview
 

ostd/src/arch/x86/device/io_port.rs

@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: MPL-2.0
 //! I/O port access.
+pub use vstd_extra::external::{group_io_port_models, valid_io_port_access};
+
 pub use x86_64::{
     instructions::port::{
         PortReadAccess as IoPortReadAccess, PortWriteAccess as IoPortWriteAccess, ReadOnlyAccess,

ostd/src/arch/x86/device/mod.rs

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MPL-2.0
 //! Device-related APIs.
 //! This module mainly contains the APIs that should exposed to the device driver like PCI, RTC
-pub mod cmos;
+/*pub mod cmos;*/
 pub mod io_port;
-pub mod serial;
+/*pub mod serial;*/

ostd/src/arch/x86/io.rs

@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: MPL-2.0
+use vstd::prelude::*;
+
 use alloc::vec::Vec;
 
 use align_ext::AlignExt;
@@ -55,6 +57,6 @@ pub(super) fn construct_io_mem_allocator_builder() -> IoMemAllocatorBuilder {
     // SAFETY: The range is guaranteed not to access physical memory.
     unsafe { IoMemAllocatorBuilder::new(ranges) }
 }
-
 /// Port I/O definition reference: <https://bochs.sourceforge.io/techspec/PORTS.LST>.
+#[verus_verify]
 pub const MAX_IO_PORT: u16 = u16::MAX;

ostd/src/arch/x86/mod.rs

@@ -1,16 +1,16 @@
 // SPDX-License-Identifier: MPL-2.0
 //! Platform-specific code for the x86 platform.
 /*pub mod boot;
-pub(crate) mod cpu;
+pub(crate) mod cpu;*/
 pub mod device;
-pub(crate) mod ex_table;
+/*pub(crate) mod ex_table;*/
 pub(crate) mod io;
-pub(crate) mod iommu;*/
+/*pub(crate) mod iommu;*/
 pub(crate) mod irq;
 /* pub(crate) mod kernel; */
 pub(crate) mod mm;
-/*pub(crate) mod pci;
-pub mod qemu;
+pub(crate) mod pci;
+/*pub mod qemu;
 pub(crate) mod serial;
 pub(crate) mod task; */
 pub mod timer;
@@ -212,7 +212,7 @@ pub(crate) fn enable_cpu_features() {
             *efer |= EferFlags::NO_EXECUTE_ENABLE;
         });
     }
-}
+}*/
 
 /// Inserts a TDX-specific code block.
 ///
@@ -251,4 +251,3 @@ macro_rules! if_tdx_enabled {
 }
 
 pub use if_tdx_enabled;
-*/

ostd/src/arch/x86/pci.rs

@@ -1,30 +1,64 @@
 // SPDX-License-Identifier: MPL-2.0
 //! PCI bus access
+use vstd::prelude::*;
+
 use super::device::io_port::{ReadWriteAccess, WriteOnlyAccess};
 use crate::{bus::pci::PciDeviceLocation, io::IoPort, prelude::*};
 
-static PCI_ADDRESS_PORT: IoPort<u32, WriteOnlyAccess> = unsafe { IoPort::new(0x0CF8) };
-static PCI_DATA_PORT: IoPort<u32, ReadWriteAccess> = unsafe { IoPort::new(0x0CFC) };
+verus! {
+
+broadcast use super::device::io_port::group_io_port_models;
+// Original Rust: static PCI_ADDRESS_PORT: IoPort<u32, WriteOnlyAccess> = unsafe { IoPort::new(0x0CF8) };
+
+exec static PCI_ADDRESS_PORT: IoPort<u32, WriteOnlyAccess>
+    ensures
+        PCI_ADDRESS_PORT.well_formed(),
+{
+    unsafe { IoPort::new(0x0CF8) }
+}
+
+// Original Rust: static PCI_DATA_PORT: IoPort<u32, ReadWriteAccess> = unsafe { IoPort::new(0x0CFC) };
+exec static PCI_DATA_PORT: IoPort<u32, ReadWriteAccess>
+    ensures
+        PCI_DATA_PORT.well_formed(),
+{
+    unsafe { IoPort::new(0x0CFC) }
+}
 
+} // verus!
+#[verus_verify]
 const BIT32_ALIGN_MASK: u32 = 0xFFFC;
 
+#[verus_verify]
+#[verus_spec(result => ensures result is Ok)]
 pub(crate) fn write32(location: &PciDeviceLocation, offset: u32, value: u32) -> Result<()> {
     PCI_ADDRESS_PORT.write(encode_as_port(location) | (offset & BIT32_ALIGN_MASK));
     PCI_DATA_PORT.write(value.to_le());
     Ok(())
 }
 
+#[verus_verify]
+#[verus_spec(result => ensures result is Ok)]
 pub(crate) fn read32(location: &PciDeviceLocation, offset: u32) -> Result<u32> {
     PCI_ADDRESS_PORT.write(encode_as_port(location) | (offset & BIT32_ALIGN_MASK));
     Ok(PCI_DATA_PORT.read().to_le())
 }
 
+#[verus_verify]
+#[verus_spec(returns true)]
 pub(crate) fn has_pci_bus() -> bool {
     true
 }
 
+#[verus_verify]
 pub(crate) const MSIX_DEFAULT_MSG_ADDR: u32 = 0xFEE0_0000;
 
+#[verus_verify]
+#[verus_spec(returns
+    MSIX_DEFAULT_MSG_ADDR | 0b1_1000
+        | ((remapping_index & 0x7FFF) << 5)
+        | ((remapping_index & 0x8000) >> 13),
+)]
 pub(crate) fn construct_remappable_msix_address(remapping_index: u32) -> u32 {
     // Use remappable format. The bits[4:3] should be always set to 1 according to the manual.
     let mut address = MSIX_DEFAULT_MSG_ADDR | 0b1_1000;
@@ -37,6 +71,13 @@ pub(crate) fn construct_remappable_msix_address(remapping_index: u32) -> u32 {
 }
 
 /// Encodes the bus, device, and function into a port address for use with the PCI I/O port.
+#[verus_verify]
+#[verus_spec(returns
+    (1u32 << 31)
+        | ((location.bus as u32) << 16)
+        | (((location.device as u32) & 0b11111) << 11)
+        | (((location.function as u32) & 0b111) << 8),
+)]
 fn encode_as_port(location: &PciDeviceLocation) -> u32 {
     // 1 << 31: Configuration enable
     (1 << 31)

ostd/src/boot/memory_region.rs

@@ -261,14 +261,13 @@ impl<const LEN: usize> Default for MemoryRegionArray<LEN> {
         Self::new()
     }
 }
-/*
 impl<const LEN: usize> Deref for MemoryRegionArray<LEN> {
     type Target = [MemoryRegion];
 
     fn deref(&self) -> &Self::Target {
         &self.regions[..self.count]
     }
-}*/
+}
 #[verus_verify]
 impl<const LEN: usize> MemoryRegionArray<LEN> {
     /// Constructs an empty set.

ostd/src/boot/mod.rs

@@ -12,10 +12,10 @@ use alloc::{
     string::{String, ToString},
     vec::Vec,
 };
-
-use memory_region::{MemoryRegion, MemoryRegionArray};
+*/
+use memory_region::{/* MemoryRegion, */ MemoryRegionArray};
 use spin::Once;
-
+/*
 /// The boot information provided by the bootloader.
 pub struct BootInfo {
     /// The name of the bootloader.
@@ -38,6 +38,7 @@ pub fn boot_info() -> &'static BootInfo {
 }
 
 static INFO: Once<BootInfo> = Once::new();
+*/
 
 /// ACPI information from the bootloader.
 ///
@@ -91,6 +92,7 @@ pub(crate) struct EarlyBootInfo {
 /// The boot-time information.
 pub(crate) static EARLY_INFO: Once<EarlyBootInfo> = Once::new();
 
+/*
 /// Initializes the boot information.
 ///
 /// This function copies the boot-time accessible information to the heap to

ostd/src/bus/mod.rs

@@ -11,7 +11,7 @@ pub enum BusProbeError {
     ConfigurationSpaceError,
 }
 
-/// Initializes the bus
+/*/// Initializes the bus
 pub(crate) fn init() {
     pci::init();
-}
+}*/

ostd/src/bus/pci/device_info.rs

@@ -1,9 +1,12 @@
 // SPDX-License-Identifier: MPL-2.0
 //! PCI device Information
+use vstd::prelude::*;
+
 use core::iter;
 
-use super::cfg_space::PciDeviceCommonCfgOffset;
+/*use super::cfg_space::PciDeviceCommonCfgOffset;*/
 
+/*
 /// PCI device ID
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub struct PciDeviceId {
@@ -48,8 +51,10 @@ impl PciDeviceId {
         }
     }
 }
+*/
 
 /// PCI device Location
+#[verus_verify]
 #[derive(Debug, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)]
 pub struct PciDeviceLocation {
     /// Bus number

ostd/src/bus/pci/mod.rs

@@ -48,14 +48,15 @@
 //!     PCI_BUS.lock().register_driver(driver_a);
 //! }
 //! ```
-pub mod bus;
+/*pub mod bus;
 pub mod capability;
 pub mod cfg_space;
-pub mod common_device;
+pub mod common_device;*/
 mod device_info;
 
-pub use device_info::{PciDeviceId, PciDeviceLocation};
+pub use device_info::{/* PciDeviceId, */ PciDeviceLocation};
 
+/*
 use self::{bus::PciBus, common_device::PciCommonDevice};
 use crate::{arch::pci::has_pci_bus, sync::Mutex};
 
@@ -74,4 +75,4 @@ pub(crate) fn init() {
         };
         lock.register_common_device(device);
     }
-}
+}*/