Power Electronics Control Simulations

Three-phase inverter current control in C — from dq regulation to SVPWM and saturation recovery.

A portable two-level voltage-source inverter (VSI) controller built from C/PLECS research studies. The project combines synchronous-frame PI control, cross-coupling compensation and anti-windup with a reproducible workflow: compile the C controller, run closed-loop scenarios, and generate waveforms and response metrics.

한국어 · Control design · PLECS integration · Tests & CI

Results at a glance

Simulation setup: compiled C controller + ideal averaged three-phase RL plant, using an exact zero-order-hold plant update. Nominal parameters: 400 V DC bus, 3 Ω / 5 mH load, 100 μs sampling, 60 Hz reference, and 2000 rad/s current-loop bandwidth. Current commands are amplitude-invariant dq values.

Scenario	Applied event	Settling time
Current tracking	q-axis command 0 → 30 A at 20 ms	2.2 ms
Load disturbance	Resistance 3 → 4.5 Ω at 60 ms, with controller gains held constant	4.1 ms
Saturation recovery	q-axis command 150 A during 20–60 ms, then 30 A	7.6 ms

Settling time is measured from each event until both dq axes remain within ±0.6 A of their final targets for the rest of the run. Phase duties stay within 0–1 across all three scenarios. See the metrics and CSV traces.

Control implementation

• dq current regulation: Clarke/Park transforms, PI loops and cross-coupling feedforward.
• SVPWM and voltage limiting: min/max common-mode injection and vector scaling that preserves voltage-vector direction during saturation.
• Anti-windup: back-calculation using applied dq voltage to support recovery from sustained saturation.
• Reusable C core: independent per-instance state, explicit initialization/reset and input validation.
• PLECS adapter: DLL lifecycle handling and port mapping, with ABI and lifecycle smoke tests.

flowchart LR
    I[Phase currents] --> T[Clarke / Park]
    T --> P[dq PI + decoupling]
    R[Current reference] --> P
    P --> M[Inverse transforms + SVPWM]
    M --> D[Bounded phase duties]
    D --> L[Averaged RL plant]
    L --> I
    M --> A[Applied dq voltage]
    A --> W[Back-calculation anti-windup]
    W --> P

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The Python simulation calls the compiled C library directly, exercising the same control core exposed by the adapter. Design notes cover coordinate conventions, equations, gains and sample timing.

Run it locally

Requirements: Python 3.10+ and a C11 compiler. Use Visual Studio 2022 with the C++ workload on Windows, or GCC/Clang on Linux/macOS. The numerical workflow runs with Python and the compiler alone.

python scripts/build.py --plecs-include legacy/include
python -m unittest discover -s tests -v
python scripts/audit_assets.py
python scripts/simulate.py --no-plot

This builds the controller and adapter, runs tests, checks archived assets, and regenerates numerical results. The archived header supports adapter smoke tests; PLECS integration instructions describe building with your installed PLECS header and mapping the ports.

To generate the figure as well:

python -m venv .venv
# Windows PowerShell: .\.venv\Scripts\Activate.ps1
# Linux/macOS: source .venv/bin/activate
python -m pip install -r requirements.txt
python scripts/simulate.py

Outputs are saved in results/; compiled artifacts go into build/.

Verification and research assets

The test suite covers coordinate-transform round trips, 1,440 modulation vectors, duty bounds, input validation, reset and instance isolation, adapter lifecycle, and three closed-loop scenarios. Closed-loop checks require each dq-axis error to be below 0.5 A RMS over the final 10 ms. A separate diagnostic captures a low-modulation issue in the archived NPC source. GitHub Actions runs the build and verification workflow on Windows and Ubuntu.

Location	Contents
src/	Portable two-level VSI control core
plecs/	PLECS DLL adapter
scripts/ / tests/	Build, simulation, asset audit and automated verification
results/	Waveforms, CSV traces and response metrics
legacy/	Preserved two-level PI/SVPWM and three-level NPC PLL/SVPWM/DPWM research sources
models/	Three PLECS research models and 12 device thermal XML definitions

The archive preserves the research starting point alongside the reusable controller and verification tools added here. Project history records source mappings, changes, model assumptions and open research issues; the asset manifest provides file fingerprints and dependency details.

Portfolio context

Alongside phil-control and phil-simulation, this project explores the electrical current-control layer underlying motor-driven systems: coordinate transforms, discrete-time feedback, modulation and actuator saturation.

Attribution

The archived PLECS header retains its Plexim copyright, and the thermal files retain their vendor metadata. Licensing and attribution for inherited materials are documented in THIRD_PARTY_NOTICES.md.