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A Multiplatform Benchmark for Memory System Characterization
Traditional memory benchmarks report isolated metrics such as peak bandwidth or idle latency, which often fail to capture how memory systems behave under realistic workloads. Mess (Memory Stress) addresses this limitation by characterizing memory performance through bandwidth-latency curves that cover the full range of memory traffic intensity, from unloaded to fully saturated.
This approach reveals critical insights:
- Memory writes degrade performance significantly compared to reads
- Systems typically saturate at 70-90% of theoretical maximum bandwidth
- Latency ranges from 85-130ns when idle to 200-600ns+ under saturation
Mess provides a holistic, close-to-hardware view of memory system behavior, enabling researchers and engineers to understand real-world performance characteristics that standard benchmarks miss.
MICRO 2024 Best Paper Runner-Up: The Mess methodology was published at the 57th IEEE/ACM International Symposium on Microarchitecture.
For a detailed explanation of the benchmark methodology, see the Memory BSC Tools page.
Mess 2.0 provides an integrated workflow for memory system characterization, from benchmarking to application profiling:
Start with the Mess benchmark to characterize your memory system. The benchmark generates bandwidth-latency curves that reveal how your system behaves under varying load—from idle to fully saturated. These curves are immediately useful for comparing different systems, analyzing different read/write ratios, and understanding memory behavior across the full traffic intensity spectrum.
To overlay your applications onto these curves, you need consistent performance counter measurements. The Mess profiler automates this by detecting available counters and running profiling tools like perf, likwid, vtune, or others with the correct configuration—ensuring your application measurements align with the benchmark data.
Finally, visualize everything with the Plotter-parser. This tool generates publication-quality plots as well as CSV and JSON files containing the parsed bandwidth-latency curves, making it easy to identify memory bottlenecks and compare system configurations.
Behind the scenes, all measurements use the Traffic generator—the same low-level engine that generates precise memory traffic patterns at the assembly level. You can also use this component independently for custom microbenchmarks or specialized testing scenarios.
- Tutorials and Slides: mess.bsc.es/tutorials
- Detailed Methodology: memory.bsc.es/tools/mess-benchmark
- Installation - Build and install Mess on your system
- FAQ - Common issues and troubleshooting
- Mess Benchmark - Running the core benchmark
- Mess profiler - Profiling application memory bandwidth
- Plotter-parser - Visualizing measurement results
- Traffic generator - The internal engine for precise memory traffic generation
These pages guide you through practical workflows for running Mess and analyzing results:
- Understanding CLI arguments - Experimenting with flags, cores, and NUMA binding
- Iterative debugging - Step-by-step validation workflow
- Adaptive pause discovery - Automatic curve-guided pause selection
- Understand output - Output file formats and interpretation
- Huge memory pages - TLB optimization and huge page usage
- Temporal vs Non-Temporal stores - Non-temporal store behavior
- Load-store vs Read-write - CPU operations vs memory controller traffic
- Traffic generator setup - Configuring the traffic generation kernel
- Instruction sampling - PEBS/SPE latency sampling from traffic-generator loads
- Architecture support - Adding support for new systems
- Changelog - Release history (see CHANGELOG.md)
Mess is developed by the Memory Systems Team at the Barcelona Supercomputing Center (BSC), focused on the design and evaluation of next-generation memory architectures for HPC and AI.
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Victor Xirau Guardans Main Mess 2.0 developer victor.xirau@bsc.es |
Pouya Esmaili Dokht Mess Paper author pouya.esmaili@bsc.es |
If you use Mess in your research, please cite:
@inproceedings{esmaili2024mess,
title = {A Mess of Memory System Benchmarking, Simulation and Application Profiling},
author = {Esmaili-Dokht, Pouya and Sgherzi, Francesco and Girelli, Valeria Soldera
and Boixaderas, Isaac and Carmin, Mariana and Monemi, Alireza
and Armejach, Adria and Mercadal, Estanislao and Llort, German
and Radojkovi{\'c}, Petar and Moreto, Miquel and Gim{\'e}nez, Judit
and Martorell, Xavier and Ayguad{\'e}, Eduard and Labarta, Jesus
and Confalonieri, Emanuele and Dubey, Rishabh and Adlard, Joshua},
booktitle = {Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)},
pages = {136--152},
year = {2024},
publisher = {IEEE}
}- Email: mess@bsc.es
- Issues: GitHub Issues
If you need documentation on a specific aspect of the Mess Benchmark that is not currently covered in this wiki, please reach out via email. We are happy to expand the documentation based on user needs.
- Mess Benchmark - The original implementation of the Mess benchmark.
- Mess Simulator - Analytical memory model using bandwidth-latency curves.
- Mess-Paraver - Integration with Paraver for visualization.
- Mess Paper - Esmaili-Dokht, P., Sgherzi, F., Girelli, V. S., Boixaderas, I., Carmin, M., Monemi, A., Armejach, A., Mercadal, E., Llort, G., Radojković, P., Moreto, M., Giménez, J., Martorell, X., Ayguadé, E., Labarta, J., Confalonieri, E., Dubey, R., & Adlard, J. (2024). A mess of memory system benchmarking, simulation and application profiling. In Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture (MICRO) (pp. 136-152). IEEE.
Mess Benchmark is released under the BSD 3-Clause License
