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  1. Implementation-of-AES-Encryption-and-Decryption-using-Verilog--Xilinx-ISE-14.7 Implementation-of-AES-Encryption-and-Decryption-using-Verilog--Xilinx-ISE-14.7 Public

    Developed a hierarchical AES-128 RTL implementation in Verilog HDL, integrating encryption/decryption, Key Expansion, UART transmission, and modular AES transformations. Verified functionality usin…

    Verilog

  2. Implementation-and-RTL-Design-of-DMA-Controller-using-Verilog-in-Xilinx-ISE-14.7 Implementation-and-RTL-Design-of-DMA-Controller-using-Verilog-in-Xilinx-ISE-14.7 Public

    Designed FSM-based DMA controller in Verilog for efficient memory transfer, reducing CPU dependency and improving system throughput

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  3. mini_soc mini_soc Public

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  4. RTL_TO_GDSII_cmos_inverter RTL_TO_GDSII_cmos_inverter Public

    RTL-to-GDSII implementation of a CMOS inverter using Verilog, Yosys, OpenROAD, Magic, KLayout, and OpenSTA with synthesis, floorplanning, placement, routing, DRC, and LVS verification.

    Verilog

  5. SPM SPM Public

    Parameterized Serial-Parallel Multiplier implemented in Verilog and taken through a complete RTL-to-GDSII ASIC flow using OpenLane, Yosys, OpenROAD, OpenSTA, and SKY130, with post-RCX STA, power an…

    Verilog

  6. RISC-V-Based-SoC-Subsystem-with-AXI4-Lite-Interconnect RISC-V-Based-SoC-Subsystem-with-AXI4-Lite-Interconnect Public

    Complete RTL-to-GDSII implementation of a RISC-V based SoC subsystem with AXI4-Lite interconnect, integrating PicoRV32, ROM, SRAM, and UART using SKY130, OpenLane, OpenROAD, Yosys, and OpenSTA.

    Verilog