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Migrate Breakpoint to rocket #10

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1fc8658
rename breakpoint
midnighter95 Apr 29, 2023
3b506c6
migrate to rocket
midnighter95 May 8, 2023
f3da5f6
remove
midnighter95 May 8, 2023
2419538
reformat and clean
midnighter95 May 8, 2023
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107 changes: 3 additions & 104 deletions diplomatic/src/rocket/CSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -15,49 +15,6 @@ import scala.collection.mutable.LinkedHashMap
import Instructions._
import CustomInstructions._

class MStatus extends Bundle {
// not truly part of mstatus, but convenient
val debug = Bool()
val cease = Bool()
val wfi = Bool()
val isa = UInt(32.W)

val dprv = UInt(PRV.SZ.W) // effective prv for data accesses
val dv = Bool() // effective v for data accesses
val prv = UInt(PRV.SZ.W)
val v = Bool()

val sd = Bool()
val zero2 = UInt(23.W)
val mpv = Bool()
val gva = Bool()
val mbe = Bool()
val sbe = Bool()
val sxl = UInt(2.W)
val uxl = UInt(2.W)
val sd_rv32 = Bool()
val zero1 = UInt(8.W)
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
val mxr = Bool()
val sum = Bool()
val mprv = Bool()
val xs = UInt(2.W)
val fs = UInt(2.W)
val mpp = UInt(2.W)
val vs = UInt(2.W)
val spp = UInt(1.W)
val mpie = Bool()
val ube = Bool()
val spie = Bool()
val upie = Bool()
val mie = Bool()
val hie = Bool()
val sie = Bool()
val uie = Bool()
}

class MNStatus extends Bundle {
val mpp = UInt(2.W)
val zero3 = UInt(3.W)
Expand Down Expand Up @@ -141,64 +98,6 @@ class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
val ppn = UInt((maxPAddrBits - pgIdxBits).W)
}

object PRV
{
val SZ = 2
val U = 0
val S = 1
val H = 2
val M = 3
}

object CSR
{
// commands
val SZ = 3
def X = BitPat.dontCare(SZ)
def N = 0.U(SZ.W)
def R = 2.U(SZ.W)
def I = 4.U(SZ.W)
def W = 5.U(SZ.W)
def S = 6.U(SZ.W)
def C = 7.U(SZ.W)

// mask a CSR cmd with a valid bit
def maskCmd(valid: Bool, cmd: UInt): UInt = {
// all commands less than CSR.I are treated by CSRFile as NOPs
cmd & ~Mux(valid, 0.U, CSR.I)
}

val ADDRSZ = 12

def modeLSB: Int = 8
def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ)
def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB)

def busErrorIntCause = 128
def debugIntCause = 14 // keep in sync with MIP.debug
def debugTriggerCause = {
val res = debugIntCause
require(!(Causes.all contains res))
res
}
def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause
def rnmiBEUCause = 12

val firstCtr = CSRs.cycle
val firstCtrH = CSRs.cycleh
val firstHPC = CSRs.hpmcounter3
val firstHPCH = CSRs.hpmcounter3h
val firstHPE = CSRs.mhpmevent3
val firstMHPC = CSRs.mhpmcounter3
val firstMHPCH = CSRs.mhpmcounter3h
val firstHPM = 3
val nCtr = 32
val nHPM = nCtr - firstHPM
val hpmWidth = 40

val maxPMPs = 16
}

class PerfCounterIO(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val eventSel = Output(UInt(xLen.W))
Expand Down Expand Up @@ -278,7 +177,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
val rocc_interrupt = Input(Bool())
val interrupt = Output(Bool())
val interrupt_cause = Output(UInt(xLen.W))
val bp = Output(Vec(nBreakpoints, new BP))
val bp = Output(Vec(nBreakpoints, new BP(p(XLen),coreParams.mcontextWidth, coreParams.scontextWidth,coreParams.useBPWatch, vaddrBits )))
val pmp = Output(Vec(nPMPs, new PMP))
val counters = Vec(nPerfCounters, new PerfCounterIO)
val csrw_counter = Output(UInt(CSR.nCtr.W))
Expand Down Expand Up @@ -458,7 +357,7 @@ class CSRFile(
val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W)))

val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP(p(XLen),coreParams.mcontextWidth, coreParams.scontextWidth,coreParams.useBPWatch, vaddrBits )))
val reg_pmp = Reg(Vec(nPMPs, new PMPReg))

val reg_mie = Reg(UInt(xLen.W))
Expand Down Expand Up @@ -1512,7 +1411,7 @@ class CSRFile(
if (coreParams.scontextWidth == 0) bpx.sselect := false.B
}
for (bp <- reg_bp drop nBreakpoints)
bp := 0.U.asTypeOf(new BP())
bp := 0.U.asTypeOf(new BP(p(XLen),coreParams.mcontextWidth, coreParams.scontextWidth,coreParams.useBPWatch, vaddrBits ))
for (pmp <- reg_pmp) {
pmp.cfg.res := 0.U
when (reset.asBool) { pmp.reset() }
Expand Down
2 changes: 1 addition & 1 deletion diplomatic/src/rocket/RocketCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -349,7 +349,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
val id_do_fence = WireDefault(id_rocc_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))

val bpu = Module(new BreakpointUnit(nBreakpoints))
val bpu = Module(new BreakpointUnit(nBreakpoints,p(XLen),coreParams.mcontextWidth, coreParams.scontextWidth,coreParams.useBPWatch, vaddrBits ))
bpu.io.status := csr.io.status
bpu.io.bp := csr.io.bp
bpu.io.pc := ibuf.io.pc
Expand Down
89 changes: 70 additions & 19 deletions diplomatic/src/rocket/Breakpoint.scala → rocket/src/Breakpoint.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -4,16 +4,67 @@ package org.chipsalliance.rocket

import chisel3._
import chisel3.util.{Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.util._

class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
import org.chipsalliance.rocket.util._

//todo: remove this
object PRV
{
val SZ = 2
val U = 0
val S = 1
val H = 2
val M = 3
}
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midnighter95 marked this conversation as resolved.
//todo: remove this
class MStatus extends Bundle {
Comment thread
midnighter95 marked this conversation as resolved.
// not truly part of mstatus, but convenient
val debug = Bool()
val cease = Bool()
val wfi = Bool()
val isa = UInt(32.W)

val dprv = UInt(PRV.SZ.W) // effective prv for data accesses
val dv = Bool() // effective v for data accesses
val prv = UInt(PRV.SZ.W)
val v = Bool()

val sd = Bool()
val zero2 = UInt(23.W)
val mpv = Bool()
val gva = Bool()
val mbe = Bool()
val sbe = Bool()
val sxl = UInt(2.W)
val uxl = UInt(2.W)
val sd_rv32 = Bool()
val zero1 = UInt(8.W)
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
val mxr = Bool()
val sum = Bool()
val mprv = Bool()
val xs = UInt(2.W)
val fs = UInt(2.W)
val mpp = UInt(2.W)
val vs = UInt(2.W)
val spp = UInt(1.W)
val mpie = Bool()
val ube = Bool()
val spie = Bool()
val upie = Bool()
val mie = Bool()
val hie = Bool()
val sie = Bool()
val uie = Bool()
}
//todo: remove util
class BPControl(xLen:Int, useBPWatch: Boolean) extends Bundle {
val ttype = UInt(4.W)
val dmode = Bool()
val maskmax = UInt(6.W)
val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W)
val action = UInt((if (coreParams.useBPWatch) 3 else 1).W)
val reserved = UInt((xLen - (if (useBPWatch) 26 else 24)).W)
val action = UInt((if (useBPWatch) 3 else 1).W)
val chain = Bool()
val zero = UInt(2.W)
val tmatch = UInt(2.W)
Expand All @@ -30,9 +81,9 @@ class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
}

class TExtra(implicit p: Parameters) extends CoreBundle()(p) {
def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13
def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34
class TExtra(xLen:Int, mcontextWidth:Int, scontextWidth:Int) extends Bundle {
def mvalueBits: Int = if (xLen == 32) mcontextWidth min 6 else mcontextWidth min 13
def svalueBits: Int = if (xLen == 32) scontextWidth min 16 else scontextWidth min 34
def mselectPos: Int = if (xLen == 32) 25 else 50
def mvaluePos : Int = mselectPos + 1
def sselectPos: Int = 0
Expand All @@ -46,14 +97,14 @@ class TExtra(implicit p: Parameters) extends CoreBundle()(p) {
val sselect = Bool()
}

class BP(implicit p: Parameters) extends CoreBundle()(p) {
val control = new BPControl
class BP(xLen: Int, mcontextWidth: Int, scontextWidth: Int, useBPWatch: Boolean, vaddrBits: Int) extends Bundle {
val control = new BPControl(xLen, useBPWatch)
val address = UInt(vaddrBits.W)
val textra = new TExtra
val textra = new TExtra(xLen, mcontextWidth, scontextWidth)

def contextMatch(mcontext: UInt, scontext: UInt) =
(if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&
(if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)
(if (mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&
(if (scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)

def mask(dummy: Int = 0) =
(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
Expand All @@ -76,14 +127,14 @@ class BPWatch (val n: Int) extends Bundle() {
val action = UInt(3.W)
}

class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {
class BreakpointUnit(n: Int, xLen: Int, mcontextWidth: Int, scontextWidth: Int, useBPWatch: Boolean, vaddrBits: Int) extends Module {
val io = IO(new Bundle {
val status = Input(new MStatus())
val bp = Input(Vec(n, new BP))
val bp = Input(Vec(n, new BP(xLen, mcontextWidth, scontextWidth, useBPWatch, vaddrBits)))
val pc = Input(UInt(vaddrBits.W))
val ea = Input(UInt(vaddrBits.W))
val mcontext = Input(UInt(coreParams.mcontextWidth.W))
val scontext = Input(UInt(coreParams.scontextWidth.W))
val mcontext = Input(UInt(mcontextWidth.W))
val scontext = Input(UInt(scontextWidth.W))
val xcpt_if = Output(Bool())
val xcpt_ld = Output(Bool())
val xcpt_st = Output(Bool())
Expand Down
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