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8fcf4fe
trying to add rom
dvirdc Jul 18, 2025
59d25b5
delete unnecessary
dvirdc Jul 18, 2025
730cc4e
delete
dvirdc Jul 18, 2025
576a9a6
fixing rom route
dvirdc Jul 18, 2025
342e860
applying top level changes
dvirdc Jul 18, 2025
458cf60
trying to put pins on met1
dvirdc Jul 18, 2025
fa1f73e
explicit
dvirdc Jul 18, 2025
4e77d06
created a rom with different metal structure to better fit with tinyt…
dvirdc Jul 18, 2025
cd05dbc
integrating rom v2 on 4x2 tiles
dvirdc Jul 19, 2025
fc10d2f
raising density to 80
dvirdc Jul 19, 2025
144a314
trying to place rom v2 on 3x4 with density 60
dvirdc Jul 19, 2025
144c728
driving cs0 from source
dvirdc Jul 19, 2025
d512f81
let openlane see USE_POWER_PINS
dvirdc Jul 19, 2025
70ec31a
another try
dvirdc Jul 19, 2025
e2ccef1
remove old rom
dvirdc Jul 19, 2025
ff9921c
trying to fix rom using v2 and power
dvirdc Jul 19, 2025
3929d44
added inout power to sha core v3
dvirdc Jul 20, 2025
8a23899
another fix
dvirdc Jul 20, 2025
00fe29d
trying this fill strategy
dvirdc Jul 20, 2025
3c16144
trying fix keep =1
dvirdc Jul 20, 2025
dd2be58
trying rom v3 with forced pins on met1 (OpenRAM error on pwr and gnd)
dvirdc Jul 20, 2025
b3cd617
trying to remove the power ring from the rom
dvirdc Jul 20, 2025
f1020c4
trying to use rom forced on met1
dvirdc Jul 20, 2025
1bacb78
tring another fix
dvirdc Jul 20, 2025
810cb64
fix
dvirdc Jul 20, 2025
4970118
added macro placement back to config
dvirdc Jul 20, 2025
c6583fb
fix
dvirdc Jul 20, 2025
9c22e11
fix error key
dvirdc Jul 20, 2025
2098ce2
trying case table
dvirdc Jul 22, 2025
848166c
3x4 tiles
dvirdc Jul 22, 2025
3766c36
try 4x2 with 94 density and 4 margins
dvirdc Jul 22, 2025
23a6c99
trying to clean ffs
dvirdc Jul 22, 2025
41bafc8
cutting clock by half trying to fit 4x2
dvirdc Jul 23, 2025
9ecd8d5
taking openlane advice density 93
dvirdc Jul 23, 2025
f27d895
trying 6x2
dvirdc Jul 27, 2025
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10 changes: 3 additions & 7 deletions info.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ project:
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "3x4" # Valid values: 1x1, 1x2, 2x2, 3x2, 3x4, 4x2, 6x2 or 8x2
tiles: "6x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 3x4, 4x2, 6x2 or 8x2

# Your top module name must start with "tt_um_". Make it unique by including your github username:
top_module: "tt_um_sha256_processor_dvirdc"
Expand All @@ -19,13 +19,9 @@ project:
source_files:
- "tt_um_sha256_processor_dvirdc.v"
- "top_gpio_sha256.v"
# - "top_uart_sha256_v2.v"
# - "top_uart_sha256.v"
- "sha256_processor.v"
- "sha256_core_v2.v"
# - "sha256_core.v"
# - "uart_rx_core.v"
# - "uart_tx_core.v"
- "sha256_core_v3.v"
- "sha256_k_constants.v"


# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
Expand Down
64 changes: 0 additions & 64 deletions rom/playground/k.hex

This file was deleted.

14 changes: 0 additions & 14 deletions rom/playground/sha256_k_rom_cfg.py

This file was deleted.

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235 changes: 0 additions & 235 deletions rom/playground/sky130_rom_krom16/sky130_rom_krom.lef

This file was deleted.

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