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fix(spi): arm the SPI slave peripheral after its DMA channels start #6291

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Merged
bugadani merged 5 commits into from
Sep 17, 2026
+19 −9
Merged

fix(spi): arm the SPI slave peripheral after its DMA channels start #6291

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14a3673
fix(spi): arm the SPI slave peripheral after its DMA channels start
molqzone Sep 9, 2026
1829bdf
Merge branch 'main' into fix/spi-slave-dma-arm-order
molqzone Sep 9, 2026
e83de51
Merge branch 'main' into fix/spi-slave-dma-arm-order
molqzone Sep 12, 2026
4b9536f
style: format SPI slave imports
molqzone Sep 16, 2026
f427482
Merge branch 'main' into fix/spi-slave-dma-arm-order
molqzone Sep 17, 2026
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28 changes: 19 additions & 9 deletions esp-hal/src/spi/slave.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -165,6 +165,8 @@ pub mod dma {
use enumset::enum_set;

use super::*;
#[cfg(not(spi_slave_dma_engine = "SPI_DMA"))]
use crate::RegisterToggle;
use crate::{
DriverMode,
dma::{Channel, DmaRxBuffer, DmaRxInterrupt, DmaTxBuffer, EmptyBuf},
Expand Down Expand Up @@ -490,35 +492,43 @@ pub mod dma {
self.info
.prepare_length_and_lines(read_buffer_len, write_buffer_len);

self.reset_dma_before_usr_cmd();

#[cfg(not(esp32))]
self.regs()
.dma_conf()
.modify(|_, w| w.dma_slv_seg_trans_en().clear_bit());

self.clear_dma_interrupts();
self.info.setup_for_flush();
self.regs().cmd().modify(|_, w| w.usr().set_bit());

if read_buffer_len > 0 {
self.reset_dma_rx_fifo();
channel.rx.start_transfer()?;
}

if write_buffer_len > 0 {
self.reset_dma_tx_fifo();
channel.tx.start_transfer()?;
}

// The SPI master owns SCLK and CS. Arm the peripheral only after
// both GDMA directions can service the first edge.
self.regs().cmd().modify(|_, w| w.usr().set_bit());

Ok(())
}

fn reset_dma_before_usr_cmd(&self) {
fn reset_dma_rx_fifo(&self) {
#[cfg(not(spi_slave_dma_engine = "SPI_DMA"))]
self.regs().dma_conf().modify(|_, w| {
w.rx_afifo_rst().set_bit();
w.buf_afifo_rst().set_bit();
w.dma_afifo_rst().set_bit()
});
self.regs()
.dma_conf()
.toggle(|w, bit| w.rx_afifo_rst().bit(bit));
}

fn reset_dma_tx_fifo(&self) {
#[cfg(not(spi_slave_dma_engine = "SPI_DMA"))]
self.regs()
.dma_conf()
.toggle(|w, bit| w.dma_afifo_rst().bit(bit));
}

fn enable_dma(&self) {
Expand Down
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