GitHub - fulingyue/CPU: 2019 Computer System Project written in verilog

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
tb		tb
.gitignore		.gitignore
ctrl.v		ctrl.v
define.v		define.v
ex.v		ex.v
ex_mem.v		ex_mem.v
hilo_reg.v		hilo_reg.v
id.v		id.v
id_ex.v		id_ex.v
if_id.v		if_id.v
inst_rom.data		inst_rom.data
inst_rom.v		inst_rom.v
mem.v		mem.v
mem_wb.v		mem_wb.v
openmips.v		openmips.v
openmips_min_sopc.v		openmips_min_sopc.v
openmips_min_sopc_tb.v		openmips_min_sopc_tb.v
pc_reg.v		pc_reg.v
reg_file.v		reg_file.v