New line after port and port map, generic and generic map

[pcdeni]

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Setting to have a new line after port and port map, generic and generic map doesn't result in the desired outcome.
Sometimes between port and port map there will be an inserted new line. The code block following it will not be indented making it look like it doesn't belong under it. This is the same for generic and generic map. However for the component instantiation part it works, as there is no "map" keyword.
Sometimes it does it properly without new line between port and map, only for the first occurrence in a file, for the consequent occurrences it fails.

component something
    generic
    (
      DEBUG_ILA_ENABLE : boolean := true
    );
    port
    (
      clk                               : in  std_logic;
      reset                             : in  std_logic
    );
  end component;

something_0 : something
  generic
  map
  (
  DEBUG_ILA_ENABLE => DEBUG_ILA_ENABLE
  )
  port
  map
  (
  clk   => clk64,
  reset => reset64
  );