Hi! Sorry, making this a 'new issue' hoping you get a notification of it: this Verilog code package has issues with place and routing on the icebreaker board (ICE40UP5k) through iCECube2, is this because LVDS DDR inputs are hardcoded to map to Bank3 of ice40 devices, and of the icebreaker board there is only banks 0,1,and 2?
thanks, J
Hi! Sorry, making this a 'new issue' hoping you get a notification of it: this Verilog code package has issues with place and routing on the icebreaker board (ICE40UP5k) through iCECube2, is this because LVDS DDR inputs are hardcoded to map to Bank3 of ice40 devices, and of the icebreaker board there is only banks 0,1,and 2?
thanks, J