feat(sky130): add logical electrical pins for SPICE export

[das-dias]

Closes doplaydo/pdks#45

Summary

• Add add_electric_pins() call to all PCells with electrical ports
• Register logical pins via component.create_pin() for each electrical port group
• No geometric pin layer changes — logical pins only (pin geometry is a TODO)
• Add gf-main optional dependency group and Makefile target for CI

Why

SPICE netlist export requires every electrical port to be wrapped in a logical
pin. Without this, ports sharing a node are not recognized as connected.

Test plan

• tests/test_electrical_pins.py — verifies logical pins registered, port_type correct
• Existing test suite passes without regression

Summary by Sourcery

Add logical electrical pins across sky130 electrical PCells and introduce parasitic extraction techfile support for SPICE export.

New Features:

• Introduce shared helper to register logical electrical pins on components without adding pin geometry.
• Add parasitic extraction techfile definition for sky130A and expose a build_tech API.
• Add tests ensuring key sky130 cells register logical pins and have electrical ports.

Enhancements:

• Wire existing diode, ESD, guard ring, via, waypoint, and MOSFET PCells through the shared logical pin helper.
• Extend project extras and Makefile to support running against gdsfactory main and gf-pex, and update lint config to exclude the new techfile.

Tests:

• Add tests validating logical pins are created and ports are typed as electrical for selected PCells.

[gemini-code-assist]

Caution

The consumer version of Gemini Code Assist on GitHub has been sunset. All code review activity has officially ceased.

[sourcery-ai]

Reviewer's Guide

Adds logical electrical pins to sky130 PCells for SPICE export, introduces a shared electrical pin helper, wires it into key device and interconnect cells, adds a sky130A parasitic extraction techfile, and updates project tooling/dependencies and tests accordingly.

Sequence diagram for electrical PCell creation with logical pins

sequenceDiagram
    actor User
    participant sky130_wire_corner as sky130.pcells.waveguides.wire_corner
    participant gdsfactory_components as gf.c
    participant Component
    participant _add_pins as sky130.pcells._common._add_pins
    participant add_electric_pins as gdsfactory.add_pins.add_electric_pins

    User->>sky130_wire_corner: wire_corner(cross_section, width, radius)
    sky130_wire_corner->>gdsfactory_components: wire_corner(cross_section, width, port_names_electrical, port_types_electrical, radius)
    gdsfactory_components-->>sky130_wire_corner: Component c
    sky130_wire_corner->>_add_pins: _add_pins(c)
    _add_pins->>add_electric_pins: add_electric_pins(c, pin_layer_map)
    add_electric_pins->>Component: create_pin() for each electrical port group
    add_electric_pins-->>_add_pins: Component with logical pins
    _add_pins-->>sky130_wire_corner: Component c
    sky130_wire_corner-->>User: Component with electrical ports and logical pins

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File-Level Changes

Change	Details	Files
Introduce shared helper to add logical electrical pins without drawing pin geometry and apply it to all relevant sky130 PCells.	Create _add_pins helper wrapping add_electric_pins with a pin_layer_map that disables pin geometry drawing by mapping pin layers to None. Wire _add_pins into MOSFET, diode, ESD, guard ring, via, waypoint, and wire_corner cells so each component registers logical pins for electrical ports. Ensure MOSFET helper _add_ports invokes _add_pins after creating electrical ports so ports are aggregated into logical pins.	sky130/pcells/_common.py sky130/pcells/mosfets.py sky130/pcells/diodes.py sky130/pcells/esd.py sky130/pcells/guard_ring.py sky130/pcells/vias.py sky130/pcells/waypoint.py sky130/pcells/waveguides.py
Add a parasitic extraction techfile for sky130A and expose it as a package API.	Implement sky130A Techfile builder defining layers, LVS computed layers, vertical process stack, and parasitic resistance/capacitance models using gf_pex. Guard import of gf_pex with a clear warning and process exit when gf_pex is not installed. Export build_tech from the sky130.pex package to allow external tools to construct the techfile.	sky130/pex/sky130A.py sky130/pex/__init__.py
Update project configuration and tooling to support gf-pex and a gf-main CI target, and adjust linting for the new PEX techfile.	Add a gf-pex optional dependency group and a gf-main extra pointing to gdsfactory main, for running against bleeding-edge tooling. Introduce a Makefile gf-main target that syncs dev+gf-main extras and installs pre-commit hooks. Exclude the generated-like sky130/pex/sky130A.py from Ruff linting to avoid style noise.	pyproject.toml Makefile
Add tests to enforce logical pin registration and electrical port typing on selected sky130 cells.	Introduce parametrized tests that instantiate a curated list of electrical cells and assert that each has at least one logical pin registered (c.pins). Verify that each tested cell exposes at least one port with port_type == 'electrical', ensuring consistency with SPICE expectations. Use the sky130.cells registry fixture to resolve cell constructors and skip tests if a cell is absent from the registry.	tests/test_electrical_pins.py

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