Support vector regalloc for RISC-V backend in ART

[GreenSeal]

Vector register allocation is already implemented for x86_64 and ARM64, but RISC-V currently lacks support. Adding this will be the step towards enabling efficient use of RISC-V vector registers

[GreenSeal]

@enh-google Could you please sign this issue on me?

[GreenSeal]

A month ago, we discussed at the Android SIG that no one had started working on the vector regalloc for RISC-V yet. I have a design proposal ready for how to support it. What would be better: to describe it here first and discuss it with you, or to prepare a patch and discuss that instead?

[enh-google]

A month ago, we discussed at the Android SIG that no one had started working on the vector regalloc for RISC-V yet. I have a design proposal ready for how to support it. What would be better: to describe it here first and discuss it with you, or to prepare a patch and discuss that instead?

(i'll forward this to the art folks and see what they say...)

[enh-google]

it looks like they've already merged some refactoring to make the implementation easier, so probably best to discuss --- any patches are likely to die in merge conflict hell :-(

[GreenSeal]

Ok, so is there any way I can get the changes that have already been merged to adapt my ideas to them? I think there's a good chance that some of the work I was planning to do has already been done

[enh-google]

if you're working with an Android partner, they'll have access to the current internal ToT. otherwise no.