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[Proc-scoped channels] Build all targets in zstd/memory with Codegen 1.5 and proc-scoped channels. #3749

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[Proc-scoped channels] Build all targets in zstd/memory with Codegen 1.5 and proc-scoped channels. #3749

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91 changes: 36 additions & 55 deletions xls/modules/zstd/memory/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -51,12 +51,15 @@ xls_dslx_library(
xls_dslx_test(
name = "common_dslx_test",
library = ":common_dslx",
tags = ["manual"],
)

COMMON_IR_CONV_ARGS = {"lower_to_proc_scoped_channels": "true"}

CLOCK_PERIOD_PS = "750"

common_codegen_args = {
CODEGEN_VERSION = "1.5"

COMMON_CODEGEN_ARGS = {
"delay_model": "asap7",
"reset": "rst",
"worst_case_throughput": "1",
Expand All @@ -71,6 +74,7 @@ common_codegen_args = {
# TODO: This should be adjusted when per channel separation of IO options is enabled
"flop_inputs_kind": "skid",
"flop_outputs_kind": "skid",
"codegen_version": CODEGEN_VERSION,
}

xls_dslx_library(
Expand All @@ -86,39 +90,36 @@ xls_dslx_library(
xls_dslx_test(
name = "axi_reader_dslx_test",
library = ":axi_reader_dslx",
tags = ["manual"],
)

# FIXME: Improve the proc to achieve CLOCK_PERIOD_PS
AXI_READER_CLOCK_PERIOD_PS = "1700"

axi_reader_codegen_args = common_codegen_args | {
AXI_READER_CODEGEN_ARGS = COMMON_CODEGEN_ARGS | {
"clock_period_ps": AXI_READER_CLOCK_PERIOD_PS,
"module_name": "axi_reader",
}

xls_dslx_verilog(
name = "axi_reader_verilog",
codegen_args = axi_reader_codegen_args,
codegen_args = AXI_READER_CODEGEN_ARGS,
dslx_top = "AxiReaderInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":axi_reader_dslx",
tags = ["manual"],
verilog_file = "axi_reader.v",
)

xls_benchmark_ir(
name = "axi_reader_opt_ir_benchmark",
src = ":axi_reader_verilog.opt.ir",
benchmark_ir_args = axi_reader_codegen_args,
tags = ["manual"],
benchmark_ir_args = AXI_READER_CODEGEN_ARGS,
)

verilog_library(
name = "axi_reader_verilog_lib",
srcs = [
":axi_reader.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -161,15 +162,14 @@ xls_dslx_library(
xls_dslx_test(
name = "axi_stream_remove_empty_dslx_test",
library = ":axi_stream_remove_empty_dslx",
tags = ["manual"],
)

xls_dslx_verilog(
name = "axi_stream_remove_empty_verilog",
codegen_args = common_codegen_args | {"module_name": "axi_stream_remove_empty"},
codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "axi_stream_remove_empty"},
dslx_top = "AxiStreamRemoveEmptyInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":axi_stream_remove_empty_dslx",
tags = ["manual"],
verilog_file = "axi_stream_remove_empty.v",
)

Expand All @@ -178,7 +178,6 @@ verilog_library(
srcs = [
":axi_stream_remove_empty.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -212,26 +211,24 @@ place_and_route(

xls_dslx_verilog(
name = "remove_empty_bytes_verilog",
codegen_args = common_codegen_args | {"module_name": "remove_empty_bytes"},
codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "remove_empty_bytes"},
dslx_top = "RemoveEmptyBytesInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":axi_stream_remove_empty_dslx",
tags = ["manual"],
verilog_file = "remove_empty_bytes.v",
)

xls_benchmark_ir(
name = "remove_empty_bytes_opt_ir_benchmark",
src = ":remove_empty_bytes_verilog.opt.ir",
benchmark_ir_args = common_codegen_args,
tags = ["manual"],
benchmark_ir_args = COMMON_CODEGEN_ARGS,
)

verilog_library(
name = "remove_empty_bytes_verilog_lib",
srcs = [
":remove_empty_bytes.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -274,31 +271,28 @@ xls_dslx_library(
xls_dslx_test(
name = "axi_stream_downscaler_dslx_test",
library = ":axi_stream_downscaler_dslx",
tags = ["manual"],
)

xls_dslx_verilog(
name = "axi_stream_downscaler_verilog",
codegen_args = common_codegen_args | {"module_name": "axi_stream_downscaler"},
codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "axi_stream_downscaler"},
dslx_top = "AxiStreamDownscalerInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":axi_stream_downscaler_dslx",
tags = ["manual"],
verilog_file = "axi_stream_downscaler.v",
)

xls_benchmark_ir(
name = "axi_stream_downscaler_opt_ir_benchmark",
src = ":axi_stream_downscaler_verilog.opt.ir",
benchmark_ir_args = common_codegen_args,
tags = ["manual"],
benchmark_ir_args = COMMON_CODEGEN_ARGS,
)

verilog_library(
name = "axi_stream_downscaler_verilog_lib",
srcs = [
":axi_stream_downscaler.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -348,25 +342,25 @@ xls_dslx_test(
# FIXME: Improve the proc to achieve CLOCK_PERIOD_PS
AXI_RAM_READER_CLOCK_PERIOD_PS = "850"

axi_ram_reader_codegen_args = common_codegen_args | {
AXI_RAM_READER_CODEGEN_ARGS = COMMON_CODEGEN_ARGS | {
"module_name": "axi_ram_reader",
"clock_period_ps": AXI_RAM_READER_CLOCK_PERIOD_PS,
"ram_configurations": "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format(
latency = 1,
ram_name = "ram",
rd_req = "axi_ram_reader__rd_req_s",
rd_resp = "axi_ram_reader__rd_resp_r",
wr_req = "axi_ram_reader__wr_req_s",
wr_resp = "axi_ram_reader__wr_resp_r",
rd_req = "_rd_req_s",
rd_resp = "_rd_resp_r",
wr_req = "_wr_req_s",
wr_resp = "_wr_resp_r",
),
}

xls_dslx_verilog(
name = "axi_ram_reader_verilog",
codegen_args = axi_ram_reader_codegen_args,
codegen_args = AXI_RAM_READER_CODEGEN_ARGS,
dslx_top = "AxiRamReaderInstWithEmptyWrites",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":axi_ram_reader_dslx",
tags = ["manual"],
verilog_file = "axi_ram_reader.v",
)

Expand All @@ -375,14 +369,12 @@ verilog_library(
srcs = [
":axi_ram_reader.v",
],
tags = ["manual"],
)

xls_benchmark_ir(
name = "axi_ram_reader_opt_ir_benchmark",
src = ":axi_ram_reader_verilog.opt.ir",
benchmark_ir_args = axi_ram_reader_codegen_args,
tags = ["manual"],
benchmark_ir_args = AXI_RAM_READER_CODEGEN_ARGS,
)

synthesize_rtl(
Expand Down Expand Up @@ -429,13 +421,12 @@ xls_dslx_library(
xls_dslx_test(
name = "mem_reader_dslx_test",
library = ":mem_reader_dslx",
tags = ["manual"],
)

# FIXME: Improve the proc to achieve CLOCK_PERIOD_PS
MEM_READER_CLOCK_PERIOD_PS = "2600"

mem_reader_codegen_args = common_codegen_args | {
mem_reader_codegen_args = COMMON_CODEGEN_ARGS | {
"clock_period_ps": MEM_READER_CLOCK_PERIOD_PS,
"module_name": "mem_reader",
}
Expand All @@ -444,8 +435,8 @@ xls_dslx_verilog(
name = "mem_reader_verilog",
codegen_args = mem_reader_codegen_args,
dslx_top = "MemReaderInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":mem_reader_dslx",
tags = ["manual"],
verilog_file = "mem_reader.v",
)

Expand All @@ -454,14 +445,12 @@ verilog_library(
srcs = [
":mem_reader.v",
],
tags = ["manual"],
)

xls_benchmark_ir(
name = "mem_reader_opt_ir_benchmark",
src = ":mem_reader_verilog.opt.ir",
benchmark_ir_args = mem_reader_codegen_args,
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -497,24 +486,22 @@ xls_dslx_verilog(
name = "mem_reader_adv_verilog",
codegen_args = mem_reader_codegen_args | {"module_name": "mem_reader_adv"},
dslx_top = "MemReaderAdvInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":mem_reader_dslx",
tags = ["manual"],
verilog_file = "mem_reader_adv.v",
)

xls_benchmark_ir(
name = "mem_reader_adv_opt_ir_benchmark",
src = ":mem_reader_adv_verilog.opt.ir",
benchmark_ir_args = mem_reader_codegen_args,
tags = ["manual"],
)

verilog_library(
name = "mem_reader_adv_verilog_lib",
srcs = [
":mem_reader_adv.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -559,31 +546,28 @@ xls_dslx_library(
xls_dslx_test(
name = "axi_writer_dslx_test",
library = ":axi_writer_dslx",
tags = ["manual"],
)

xls_dslx_verilog(
name = "axi_writer_verilog",
codegen_args = common_codegen_args | {"module_name": "axi_writer"},
codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "axi_writer"},
dslx_top = "AxiWriterInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":axi_writer_dslx",
tags = ["manual"],
verilog_file = "axi_writer.v",
)

xls_benchmark_ir(
name = "axi_writer_opt_ir_benchmark",
src = ":axi_writer_verilog.opt.ir",
benchmark_ir_args = common_codegen_args,
tags = ["manual"],
benchmark_ir_args = COMMON_CODEGEN_ARGS,
)

verilog_library(
name = "axi_writer_verilog_lib",
srcs = [
":axi_writer.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -631,7 +615,7 @@ xls_dslx_test(
library = ":axi_stream_add_empty_dslx",
)

axi_stream_add_empty_codegen_args = common_codegen_args | {
axi_stream_add_empty_codegen_args = COMMON_CODEGEN_ARGS | {
"module_name": "axi_stream_add_empty",
"pipeline_stages": "2",
"streaming_channel_data_suffix": "_data",
Expand All @@ -641,24 +625,22 @@ xls_dslx_verilog(
name = "axi_stream_add_empty_verilog",
codegen_args = axi_stream_add_empty_codegen_args,
dslx_top = "AxiStreamAddEmptyInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":axi_stream_add_empty_dslx",
tags = ["manual"],
verilog_file = "axi_stream_add_empty.v",
)

xls_benchmark_ir(
name = "axi_stream_add_empty_opt_ir_benchmark",
src = ":axi_stream_add_empty_verilog.opt.ir",
benchmark_ir_args = axi_stream_add_empty_codegen_args,
tags = ["manual"],
)

verilog_library(
name = "axi_stream_add_empty_verilog_lib",
srcs = [
":axi_stream_add_empty.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down Expand Up @@ -710,10 +692,10 @@ xls_dslx_test(

xls_dslx_verilog(
name = "mem_writer_verilog",
codegen_args = common_codegen_args | {"module_name": "mem_writer"},
codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "mem_writer"},
dslx_top = "MemWriterInst",
ir_conv_args = COMMON_IR_CONV_ARGS,
library = ":mem_writer_dslx",
tags = ["manual"],
verilog_file = "mem_writer.v",
)

Expand All @@ -722,7 +704,6 @@ verilog_library(
srcs = [
":mem_writer.v",
],
tags = ["manual"],
)

synthesize_rtl(
Expand Down
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