mem: add an MI300X-oriented HBM3 x64 interface - #8
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This commit fixes the instruction execution latency of LDS instructions based on what microbenchmarks suggest
The LDS uses 4 byte wide banks in most GPUs. This requires each 4B address to map to a bank. The previous model mapped each byte to a bank and introduced several bank conflicts. This commit fixes the bank mapping to map each 4B word to an LDS bank Change-Id: Iaca0bcd3525a31c4ae55e379bf341a1de3ef8b31
Change-Id: I6dc1c9118027434a9e0bd26cc3843d3f56d955ad
Previously, the LDS model assumed each instruction has the same bus data transfer costs. This commit updates that to use the instruction dword length instead Change-Id: Id3decd6bb6fba3c50c84377ac5c7550660113092
Previously, `GlobalMemPipeline::getNextReadyResp` only checked the absolute oldest request in the entire ComputeUnit. If this single request was incomplete, it blocked all subsequent completed requests from being processed, degrading global memory pipeline performance. This commit updates the response selection logic to pick the oldest completed request on a per-wavefront basis. This prevents a single stalled wavefront from starving the entire CU, improving overall global memory pipeline throughput. Change-Id: Ia9bfde40a1940f450aee181ab816cc47dc677644
Introduce separate fabric_clk and memory_clk for the GPUFS, replacing the single ruby_clock domain. Change-Id: I817ab2e5a215b76728fd31dcc067535fd6590126
Previously, gpu clock was not applied to the model Change-Id: Ic3e39f984bc79fc0787282bb73d004a1f474e904
Add a 64-bit HBM3 channel model sized and clocked for the public MI300X memory organization. The interface is intended to be paired by HBMCtrl, giving 128 modeled x64 channels across eight stacks. Use the public AMD MI300X capacity, interface-width, and transfer-rate data. For timings not published by AMD, derive conservative values from the Ramulator 2.1.0 HBM3_16Gb_8hi and HBM3_6400Mbps presets, scaling command timings to the slower MI300X command clock. Document the model assumptions where gem5 cannot directly represent HBM3 hierarchy or fractional command cycles.
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Add a 64-bit HBM3 channel model sized and clocked for the public MI300X memory organization. The interface is intended to be paired by HBMCtrl, giving 128 modeled x64 channels across eight stacks.
Use the public AMD MI300X capacity, interface-width, and transfer-rate data. For timings not published by AMD, derive conservative values from the Ramulator 2.1.0 HBM3_16Gb_8hi and HBM3_6400Mbps presets, scaling command timings to the slower MI300X command clock.
Unlike the generic HBM3 preset in gem5#3271 this interface is parameterized for MI300X’s existing HBMCtrl topology: eight controllers pair sixteen x64 interfaces per stack. Its capacity and burst timing reproduce 24 GB and approximately 665 GB/s per stack, or 192 GB and 5.3 TB/s across the package.