mem-ruby,configs: add a configurable GPU L3 to GPU_VIPER

configs/example/gpufs/Disjoint_VIPER.py

@@ -50,6 +50,7 @@ def __init__(self):
         super().__init__()
 
     def create(self, options, system, piobus, dma_devices):
+        self.clk_domain = system.fabric_clk
         # Disjoint network topology
         if "garnet" in options.network:
             self.network_cpu = DisjointGarnet(self)

configs/example/gpufs/mi300.py

@@ -71,17 +71,18 @@
     sh /home/gem5/load_amdgpu.sh
 elif [ ! -f /lib/modules/`uname -r`/updates/dkms/amdgpu.ko ]; then
     echo "ERROR: Missing DKMS package for kernel `uname -r`. Exiting gem5."
-    /sbin/m5 exit
+    # m5 exit
 else
     # Backward compatibility with old disk images (ROCm 6.1)
     modprobe -v amdgpu ip_block_mask=0x6f ppfeaturemask=0 dpm=0 audio=0 ras_enable=0 discovery=2
 fi
+modprobe -v amdgpu ip_block_mask=0x6f ppfeaturemask=0 dpm=0 audio=0 ras_enable=0 discovery=2
 
 echo "Running {} {}"
 echo "{}" | base64 -d > myapp
 chmod +x myapp
 ./myapp {}
-/sbin/m5 exit
+m5 exit
 """
 
 demo_runscript_with_checkpoint = """\

configs/example/gpufs/system/amdgpu.py

@@ -36,7 +36,10 @@ def createGPU(system, args):
         n_wf=args.wfs_per_simd,
         cu_per_sqc=args.cu_per_sqc,
         timing=True,
-        clk_domain=system.clk_domain,
+        clk_domain=SrcClockDomain(
+            clock=args.gpu_clock,
+            voltage_domain=VoltageDomain(voltage=args.gpu_voltage),
+        ),
         progress_interval=args.gpu_progress_interval,
     )
 

configs/example/gpufs/system/system.py

@@ -54,6 +54,8 @@ def makeGpuFSSystem(args):
         "drm_kms_helper.fbdev_emulation=0",
         "modprobe.blacklist=amdgpu",
         "modprobe.blacklist=psmouse",
+        # Tell linux to use MP table for PCI IRQs and not ACPI.
+        "pci=noacpi",
     ]
     cmdline = " ".join(boot_options)
 
@@ -73,6 +75,13 @@ def makeGpuFSSystem(args):
     )
     system.workload.object_file = binary(args.kernel)
 
+    # FADT pointing at a minimal DSDT. This prevents Linux from disabling
+    # ACPI which is needed by the WMI module which is a dependency for the
+    # amdgpu module.
+    fadt = X86ACPIFADT(dsdt=X86ACPIDSDT(), oem_id="gem5")
+    system.workload.acpi_description_table_pointer.rsdt.entries.append(fadt)
+    system.workload.acpi_description_table_pointer.xsdt.entries.append(fadt)
+
     # Set the cache line size for the entire system.
     system.cache_line_size = args.cacheline_size
 
@@ -302,6 +311,13 @@ def makeGpuFSSystem(args):
         pm4_proc.pio = system.iobus.mem_side_ports
     system_hub.pio = system.iobus.mem_side_ports
 
+    system.fabric_clk = SrcClockDomain(
+        clock=args.fabric_clock, voltage_domain=system.voltage_domain
+    )
+    system.memory_clk = SrcClockDomain(
+        clock=args.memory_clock, voltage_domain=system.voltage_domain
+    )
+
     # Full system needs special TLBs for SQC, Scalar, and vector data ports
     args.full_system = True
     GPUTLBConfig.config_tlb_hierarchy(
@@ -313,9 +329,10 @@ def makeGpuFSSystem(args):
     system.ruby.create(args, system, system.iobus, system._dma_ports)
 
     # Create a seperate clock domain for Ruby
-    system.ruby.clk_domain = SrcClockDomain(
-        clock=args.ruby_clock, voltage_domain=system.voltage_domain
-    )
+    # system.ruby.clk_domain = SrcClockDomain(
+    #     clock=args.ruby_clock, voltage_domain=system.voltage_domain
+    # )
+    system.ruby.clk_domain = system.fabric_clk
 
     # If we are using KVM cpu, enable AVX. AVX is used in some ROCm libraries
     # such as rocBLAS which is used in higher level libraries like PyTorch.

configs/ruby/GPU_VIPER.py

@@ -98,7 +98,7 @@ class L2Cache(RubyCache):
     def create(self, size, assoc, options):
         self.size = MemorySize(size)
         self.assoc = assoc
-        self.replacement_policy = TreePLRURP()
+        self.replacement_policy = BRRIPRP()
 
 
 class CPCntrl(GPU_VIPER_CorePair_Controller, CntrlBase):
@@ -165,7 +165,7 @@ def create(self, options, ruby_system, system):
         self.L1cache.dataArrayBanks = options.tcp_num_banks
         self.L1cache.tagArrayBanks = options.tcp_num_banks
         self.L1cache.create(options)
-        self.issue_latency = 1
+        self.issue_latency = options.tcp_issue_latency
         # TCP_Controller inherits this from RubyController
         self.mandatory_queue_latency = options.mandatory_queue_latency
 
@@ -295,10 +295,8 @@ def create(self, options):
             self.tagArrayBanks = 64
         else:
             self.size = MemorySize(options.tcc_size)
-            self.dataArrayBanks = (
-                256 / options.num_tccs
-            )  # number of data banks
-            self.tagArrayBanks = 256 / options.num_tccs  # number of tag banks
+            self.dataArrayBanks = options.tcc_num_banks  # number of data banks
+            self.tagArrayBanks = options.tcc_num_banks  # number of tag banks
         self.size.value = self.size.value / options.num_tccs
         if (self.size.value / int(self.assoc)) < 128:
             self.size.value = int(128 * self.assoc)
@@ -320,9 +318,11 @@ def create(self, options, ruby_system, system):
         self.L2cache.resourceStalls = options.no_tcc_resource_stalls
 
         self.ruby_system = ruby_system
-        if hasattr(options, "gpu_clock") and hasattr(options, "gpu_voltage"):
+        if hasattr(options, "fabric_clock") and hasattr(
+            options, "gpu_voltage"
+        ):
             self.clk_domain = SrcClockDomain(
-                clock=options.gpu_clock,
+                clock=options.fabric_clock,
                 voltage_domain=VoltageDomain(voltage=options.gpu_voltage),
             )
 
@@ -334,18 +334,23 @@ class L3Cache(RubyCache):
     dataArrayBanks = 16
     tagArrayBanks = 16
 
-    def create(self, options, ruby_system, system):
+    def create(self, options, ruby_system, system, num_dirs=None):
+        # num_dirs: number of directory controllers sharing this L3 pool.
+        # Defaults to options.num_dirs (CPU-side) if not specified.
+        if num_dirs is None:
+            num_dirs = options.num_dirs
         self.size = MemorySize(options.l3_size)
-        self.size.value /= options.num_dirs
+        self.size.value /= num_dirs
         self.assoc = options.l3_assoc
-        self.dataArrayBanks /= options.num_dirs
-        self.tagArrayBanks /= options.num_dirs
-        self.dataArrayBanks /= options.num_dirs
-        self.tagArrayBanks /= options.num_dirs
+        # Each directory controller owns one L3 slice. Configure the internal
+        # data and tag bank count of that slice independently of the number of
+        # directory controllers.
+        self.dataArrayBanks = options.l3_num_banks
+        self.tagArrayBanks = options.l3_num_banks
         self.dataAccessLatency = options.l3_data_latency
         self.tagAccessLatency = options.l3_tag_latency
         self.resourceStalls = False
-        self.replacement_policy = TreePLRURP()
+        self.replacement_policy = BRRIPRP()
 
 
 class L3Cntrl(GPU_VIPER_L3Cache_Controller, CntrlBase):
@@ -380,7 +385,7 @@ def connectWireBuffers(
 
 
 class DirCntrl(GPU_VIPER_Directory_Controller, CntrlBase):
-    def create(self, options, dir_ranges, ruby_system, system):
+    def create(self, options, dir_ranges, ruby_system, system, num_dirs=None):
         self.version = self.versionCount()
 
         self.response_latency = 30
@@ -391,7 +396,8 @@ def create(self, options, dir_ranges, ruby_system, system):
         )
 
         self.L3CacheMemory = L3Cache()
-        self.L3CacheMemory.create(options, ruby_system, system)
+        self.L3CacheMemory.create(options, ruby_system, system,
+                                  num_dirs=num_dirs)
 
         self.l3_hit_latency = max(
             self.L3CacheMemory.dataAccessLatency,
@@ -424,8 +430,15 @@ def connectWireBuffers(
 
 def define_options(parser):
     parser.add_argument("--num-subcaches", type=int, default=4)
+    parser.add_argument("--tcp-issue-latency", type=int, default=1)
     parser.add_argument("--l3-data-latency", type=int, default=20)
     parser.add_argument("--l3-tag-latency", type=int, default=15)
+    parser.add_argument(
+        "--l3-num-banks",
+        type=int,
+        default=16,
+        help="Number of data and tag banks in each directory L3 slice",
+    )
     parser.add_argument("--cpu-to-dir-latency", type=int, default=120)
     parser.add_argument("--gpu-to-dir-latency", type=int, default=120)
     parser.add_argument(
@@ -435,6 +448,13 @@ def define_options(parser):
         "--no-tcc-resource-stalls", action="store_false", default=True
     )
     parser.add_argument("--use-L3-on-WT", action="store_true", default=False)
+    parser.add_argument("--use-gpu-l3", action="store_true", default=False,
+                        help="Enable L3 (Infinity Cache) fills for GPU "
+                             "directory controllers")
+    parser.add_argument("--l3-exclusive", action="store_true", default=False,
+                        help="Experimental non-CDNA3 victim-cache policy: "
+                             "GPU reads consume L3 entries and fills occur "
+                             "from lower-level evictions")
     parser.add_argument("--num-tbes", type=int, default=256)
     parser.add_argument("--l2-latency", type=int, default=50)  # load to use
     parser.add_argument(
@@ -465,7 +485,17 @@ def define_options(parser):
         "--TCP_latency",
         type=int,
         default=4,
-        help="In combination with the number of banks for the "
+        help="Set tcp tag access latency. "
+        "In combination with the number of banks for the "
+        "TCP, this determines how many requests can happen "
+        "per cycle (i.e., the bandwidth)",
+    )
+    parser.add_argument(
+        "--TCP_latency_data",
+        type=int,
+        default=4,
+        help="Set tcp data access latency. "
+        "In combination with the number of banks for the "
         "TCP, this determines how many requests can happen "
         "per cycle (i.e., the bandwidth)",
     )
@@ -537,6 +567,8 @@ def define_options(parser):
         default="8",
         help="Data access latency in L2 cache",
     )
+    parser.add_argument("--fabric-clock", type=str, default="1080MHz")
+    parser.add_argument("--memory-clock", type=str, default="1000MHz")
 
 
 def construct_dirs(options, system, ruby_system, network):
@@ -545,14 +577,14 @@ def construct_dirs(options, system, ruby_system, network):
     # For an odd number of CPUs, still create the right number of controllers
     TCC_bits = int(math.log(options.num_tccs, 2))
 
+    dir_bits = int(math.log(options.num_dirs, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
     if options.numa_high_bit:
         numa_bit = options.numa_high_bit
     else:
         # if the numa_bit is not specified, set the directory bits as the
         # lowest bits above the block offset bits, and the numa_bit as the
         # highest of those directory bits
-        dir_bits = int(math.log(options.num_dirs, 2))
-        block_size_bits = int(math.log(options.cacheline_size, 2))
         numa_bit = block_size_bits + dir_bits - 1
 
     for i in range(options.num_dirs):
@@ -569,6 +601,7 @@ def construct_dirs(options, system, ruby_system, network):
 
         dir_cntrl = DirCntrl(noTCCdir=True, TCC_select_num_bits=TCC_bits)
         dir_cntrl.create(options, dir_ranges, ruby_system, system)
+        dir_cntrl.L3CacheMemory.start_index_bit = block_size_bits + dir_bits
         dir_cntrl.number_of_TBEs = options.num_tbes
         dir_cntrl.useL3OnWT = options.use_L3_on_WT
         dir_cntrl.L2isWB = options.WB_L2
@@ -631,10 +664,18 @@ def construct_gpudirs(options, system, ruby_system, network):
             xorHighBit=xor_low_bit,
         )
 
-        dir_cntrl = DirCntrl(noTCCdir=True, TCC_select_num_bits=TCC_bits)
-        dir_cntrl.create(options, [addr_range], ruby_system, system)
+        dir_cntrl = DirCntrl(
+            noTCCdir=True,
+            TCC_select_num_bits=TCC_bits,
+            clk_domain=system.fabric_clk,
+        )
+        dir_cntrl.create(options, [addr_range], ruby_system, system,
+                         num_dirs=options.dgpu_num_dirs)
+        dir_cntrl.L3CacheMemory.start_index_bit = block_size_bits + dir_bits
         dir_cntrl.number_of_TBEs = options.num_tbes
-        dir_cntrl.useL3OnWT = False
+        dir_cntrl.GPUonly = True
+        dir_cntrl.useL3OnWT = options.use_gpu_l3
+        dir_cntrl.L3Exclusive = options.l3_exclusive
         dir_cntrl.L2isWB = options.WB_L2
 
         # Connect the Directory controller to the ruby network
@@ -702,7 +743,9 @@ def construct_gpudirs(options, system, ruby_system, network):
         if issubclass(mem_type, DRAMInterface):
             if options.hbm_ctrl:
                 mem_ctrl = m5.objects.HBMCtrl(
-                    dram=dram_intf, dram_2=dram_intf_2
+                    dram=dram_intf,
+                    dram_2=dram_intf_2,
+                    clk_domain=system.memory_clk,
                 )
             else:
                 mem_ctrl = m5.objects.MemCtrl(dram=dram_intf)
@@ -780,7 +823,7 @@ def construct_tcps(options, system, ruby_system, network):
         tcp_cntrl.WB = options.WB_L1
         tcp_cntrl.disableL1 = options.noL1
         tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency
-        tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency
+        tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency_data
 
         exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % i)
         #
@@ -936,7 +979,10 @@ def construct_tccs(options, system, ruby_system, network):
     tcc_cntrl_nodes = []
 
     for i in range(options.num_tccs):
-        tcc_cntrl = TCCCntrl(l2_response_latency=options.TCC_latency)
+        tcc_cntrl = TCCCntrl(
+            l2_response_latency=options.TCC_latency,
+            clk_domain=system.fabric_clk,
+        )
         tcc_cntrl.create(options, ruby_system, system)
         tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency
         tcc_cntrl.l2_response_latency = options.TCC_latency