Skip to content

add setting for Verilog external code library path #1321

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
renyangang wants to merge 3 commits into
base: master
Choose a base branch
from

support socket comm with extern app

c9ddfe1
Select commit
Loading
Failed to load commit list.
Open

add setting for Verilog external code library path #1321

support socket comm with extern app
c9ddfe1
Select commit
Loading
Failed to load commit list.

Workflow runs completed with no jobs