[Media Common] Enable Wa to disable object capture for DG1#1895
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intel-mediadev merged 1 commit intointel:masterfrom Apr 27, 2025
Merged
[Media Common] Enable Wa to disable object capture for DG1#1895intel-mediadev merged 1 commit intointel:masterfrom
intel-mediadev merged 1 commit intointel:masterfrom
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@Jexu Inspired by the regression in Xe KMD, I'm sure the above will work together to make DG1 usable in upstream i915. |
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Linux 6.13+ and LTS releases (6.1.124+, 6.6.70+ and 6.12.9+) have included the DG1 powergate fix. @Jexu @XinfengZhang Also, if I understand correctly, the The kernel 5.16+ enables GuC submission on DG1 by default, just like it does on ADL-P/ADL-N+. From 9175ffff5ea9f2b9e956f7458d3fa38eec8f6ec8 Mon Sep 17 00:00:00 2001
From: Matthew Brost <matthew.brost@intel.com>
Date: Thu, 16 Sep 2021 09:28:18 -0700
Subject: [PATCH] drm/i915/guc: Enable GuC submission by default on DG1
Enable GuC submission by default on DG1
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210916162819.27848-5-matthew.brost@intel.com |
This Wa is needed for using DG1 with the upstream i915 kernel. Partially fixes: intel#1415 (comment) The other part needs to be fixed on KMD side by disabling HCP_POWERGATE and MFXVDENC_POWERGATE for DG1. Unlike TGLx, DG1 doesn't support sub-pipe PG and setting these bits will cause HEVC and VP9 decoding failure. See also https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381 Signed-off-by: nyanmisaka <nst799610810@gmail.com>
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Hi @XinfengZhang, could you spare a minute to merge this simple fix? DG1 is now available in both i915 & Xe KMD in upstream linux. See also #1920 |
XinfengZhang
approved these changes
Apr 25, 2025
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This Wa is needed for using DG1 with the upstream i915 kernel.
Partially fixes:
#1415 (comment)
The other part needs to be fixed on KMD side by disabling
HCP_POWERGATEandMFXVDENC_POWERGATEfor DG1. Unlike TGLx, DG1 doesn't support sub-pipe PG and setting these bits will cause HEVC and VP9 decoding failure.See also https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381