A lightweight multi-agent framework for hardware RTL generation + verification:
- Decomposer Agent: breaks a high-level requirement into a module tree/contracts
- RTL Coder: generates Verilog RTL for leaf modules
- TB Generator: generates a top-level testbench based on the real DUT ports
- Auto-Rework Loop: runs
iverilogand, on compile failures, invokes a Rework Agent to overwrite the RTL bundle and retry (up to 5 attempts)
pip install -r requirements.txtInstall Icarus Verilog so iverilog and vvp are available in your PATH.
python -m orchestrator.run_mvp --mock --user-goal-file user_goal.txt --no-progressOutputs are written to ./output/<timestamp>/:
hdl_bundle.v(generated RTL bundle)tb_top.v(generated testbench)simulation.log(build/run output)sim.vvp(iverilog output)
Create a local .env (do not commit it) based on .env.example.
Defaults:
- If
OPENAI_API_KEYis set: uses OpenAI-compatible Chat Completions withLLM_MODEL=gpt-4o. - If
DEEPSEEK_API_KEYis set (and OpenAI key is empty): uses DeepSeek OpenAI-compatible API withLLM_MODEL=deepseek-chat. - If both are set: prefers OpenAI.
You can override via LLM_PROVIDER, LLM_API_URL, LLM_MODEL, LLM_TEMPERATURE (see orchestrator/config.py).
orchestrator/core runtimeprompts/prompt registry (required)user_goal.txtexample goal you can edit
