kako-jun · kako-jun · Sep 17, 2026 · Sep 17, 2026 · Sep 17, 2026 · Sep 17, 2026
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -2,6 +2,19 @@
 
 All notable changes to this project will be documented in this file.
 
+## [2.5.0] - 2026-09-17
+
+### Added
+- Extension implication and composition: extensions that are architecturally implied by others actually present, but that `/proc/cpuinfo` didn't enumerate directly (e.g. `Zba`+`Zbb`+`Zbs` present but `B` missing, `M` present but `Zmmul` missing), are now computed and shown in parentheses, e.g. `Ext: I M A F D C V (B)` / `Z-Multiply: (Zmmul)`. Sourced from LLVM mainline's `RISCVFeatures.td` `Implies` tables and the RISC-V ISA manual's shorthand-extension definitions (#10)
+- `ExtensionInfo.derived` / `ExtensionEntry.derived` fields (additive) marking whether an extension was reported directly (`false`) or inferred (`true`); `--json` output includes the same field
+
+### Changed
+- `--help` now includes a line explaining the parentheses notation for derived extensions
+- `riscfetch-core` bumped to **3.0.0**: adding the required `derived: bool` field to the
+  public, non-`#[non_exhaustive]` `ExtensionEntry`/`ExtensionInfo` structs is additive for
+  JSON consumers but breaks any Rust caller constructing these structs by literal, so
+  semver requires a major bump for the library even though the CLI itself is 2.5.0
+
 ## [2.4.0] - 2026-09-17
 
 ### Added

diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -3,7 +3,7 @@ members = ["crates/riscfetch-core", "crates/riscfetch-cli"]
 resolver = "2"
 
 [workspace.package]
-version = "2.4.0"
+version = "2.5.0"
 edition = "2021"
 authors = ["kako-jun"]
 license = "MIT"

diff --git a/README.ja.md b/README.ja.md
@@ -68,9 +68,10 @@ riscfetch -l pine64    # Pine64 ロゴを使用
 
 ```
 ISA:        rv64imafdcv_zicsr_zifencei_zba_zbb_zbs_sstc...
-Ext:        I M A F D C V
+Ext:        I M A F D C V (B)
 Z-Base:     Zicsr Zifencei Zicntr Zihpm
 Z-Bit:      Zba Zbb Zbc Zbs
+Z-Multiply: (Zmmul)
 Z-Vector:   Zvl128b Zvl256b
 S-Sup:      Sstc
 Vector:     Enabled, VLEN>=256
@@ -88,6 +89,8 @@ Uptime:     3h 42m
 User:       user@visionfive2
 ```
 
+**括弧付き**で表示される拡張（`(B)` や `(Zmmul)` など）は、`/proc/cpuinfo` に直接は載っていないものの、他に存在する拡張から導かれる（含意される）拡張です。例えば `Zba`+`Zbb`+`Zbs` が揃っていれば `B` を、`M` があれば `Zmmul` を意味します。それ以外はカーネルが実際に列挙した拡張そのままです。
+
 ## オプション
 
 | フラグ | 説明 |

diff --git a/README.md b/README.md
@@ -68,9 +68,10 @@ Extensions are grouped by category:
 
 ```
 ISA:        rv64imafdcv_zicsr_zifencei_zba_zbb_zbs_sstc...
-Ext:        I M A F D C V
+Ext:        I M A F D C V (B)
 Z-Base:     Zicsr Zifencei Zicntr Zihpm
 Z-Bit:      Zba Zbb Zbc Zbs
+Z-Multiply: (Zmmul)
 Z-Vector:   Zvl128b Zvl256b
 S-Sup:      Sstc
 Vector:     Enabled, VLEN>=256
@@ -88,6 +89,8 @@ Uptime:     3h 42m
 User:       user@visionfive2
 ```
 
+Extensions shown in **parentheses**, like `(B)` or `(Zmmul)`, were not reported directly by `/proc/cpuinfo` but are implied by other extensions that are present — e.g. `Zba`+`Zbb`+`Zbs` implies `B`, and `M` implies `Zmmul`. Everything else is exactly what the kernel enumerated.
+
 ## Options
 
 | Flag | Description |

diff --git a/README.zh-CN.md b/README.zh-CN.md
@@ -68,9 +68,10 @@ riscfetch -l pine64    # 使用 Pine64 logo
 
 ```
 ISA:        rv64imafdcv_zicsr_zifencei_zba_zbb_zbs_sstc...
-Ext:        I M A F D C V
+Ext:        I M A F D C V (B)
 Z-Base:     Zicsr Zifencei Zicntr Zihpm
 Z-Bit:      Zba Zbb Zbc Zbs
+Z-Multiply: (Zmmul)
 Z-Vector:   Zvl128b Zvl256b
 S-Sup:      Sstc
 Vector:     Enabled, VLEN>=256
@@ -88,6 +89,8 @@ Uptime:     3h 42m
 User:       user@visionfive2
 ```
 
+带**括号**显示的扩展（例如 `(B)` 或 `(Zmmul)`）并未直接出现在 `/proc/cpuinfo` 中，而是根据当前已有的其他扩展推导（隐含）得出的。例如 `Zba`+`Zbb`+`Zbs` 齐全即隐含 `B`，有 `M` 即隐含 `Zmmul`。其余扩展均为内核实际列出的原始内容。
+
 ## 选项
 
 | 参数 | 说明 |

diff --git a/crates/riscfetch-cli/Cargo.toml b/crates/riscfetch-cli/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscfetch"
-version = "2.4.0"
+version = "2.5.0"
 edition = "2021"
 authors = ["kako-jun"]
 description = "RISC-V architecture information display tool - Show off your RISC-V setup!"
@@ -11,7 +11,7 @@ categories = ["command-line-utilities"]
 readme = "../../README.md"
 
 [dependencies]
-riscfetch-core = { path = "../riscfetch-core", version = "2.3.0" }
+riscfetch-core = { path = "../riscfetch-core", version = "3.0.0" }
 clap = { version = "4.5", features = ["derive"] }
 colored = "2.1"
 serde_json = "1.0"

diff --git a/crates/riscfetch-cli/SPEC.md b/crates/riscfetch-cli/SPEC.md
@@ -67,10 +67,11 @@ Extensions are grouped by category for better readability:
 
 ```
 ISA:        rv64imafdcv_zicbom_zicboz_zicntr_zicsr_zifencei_...
-Ext:        I M A F D C V
+Ext:        I M A F D C V (B)
 Z-Base:     Zicsr Zifencei Zicntr Zihpm
 Z-Bit:      Zba Zbb Zbc Zbs
 Z-Cache:    Zicbom Zicboz
+Z-Multiply: (Zmmul)
 Z-Vector:   Zvl128b Zvl256b
 S-Sup:      Sstc
 Vector:     Enabled, VLEN>=256
@@ -88,14 +89,19 @@ Uptime:     3h 42m
 User:       user@spacemit
 ```
 
+Extensions shown in **parentheses** (e.g. `(B)`, `(Zmmul)`) were not reported directly by
+`/proc/cpuinfo` but are implied by other extensions that are present — see "Derived
+Extensions" in `riscfetch-core/SPEC.md` for the full implication/composition rules and
+sources. Everything not in parentheses is exactly what the kernel enumerated.
+
 ### Field Definitions
 
 | Field | Description | Example |
 |-------|-------------|---------|
 | ISA | Full ISA string from /proc/cpuinfo | `rv64imafdc_zicsr_zifencei` |
-| Ext | Standard extensions (space-separated) | `I M A F D C V` |
-| Z-{Category}: | Z-extensions grouped by category | `Z-Bit: Zba Zbb Zbc Zbs` |
-| S-{Category}: | S-extensions (privileged) by category | `S-Sup: Sstc` |
+| Ext | Standard extensions (space-separated); derived ones in parentheses | `I M A F D C V (B)` |
+| Z-{Category}: | Z-extensions grouped by category; derived ones in parentheses | `Z-Bit: Zba Zbb Zbc Zbs` |
+| S-{Category}: | S-extensions (privileged) by category; derived ones in parentheses | `S-Sup: Sstc` |
 | Vector | Vector extension status and VLEN | `Enabled, VLEN>=256` or empty |
 | Harts | Number of hardware threads | `4 harts` |
 | HW IDs | Hardware identifiers | `vendor:0x489 arch:0x... impl:0x...` |
@@ -153,6 +159,7 @@ Extensions:
   D          Double-Precision Float
   C          Compressed (16-bit)
   V          Vector (SIMD)
+  (B)        Bit Manipulation
 
 Z-Extensions (Base):
   Zicsr      CSR Instructions
@@ -169,6 +176,9 @@ Z-Extensions (Bit Manipulation):
 Z-Extensions (Cryptography):
   Zkt        Data-Indep Timing
 
+Z-Extensions (Multiply):
+  (Zmmul)    Multiply Only (no Div)
+
 Z-Extensions (Vector):
   Zvl128b    VLEN >= 128 bits
   Zvl256b    VLEN >= 256 bits
@@ -178,6 +188,9 @@ S-Extensions (Supervisor):
   Sstc       Supervisor Timer
 ```
 
+As in compact mode, extensions in parentheses (`(B)`, `(Zmmul)`) are derived via
+implication/composition rather than reported directly.
+
 ---
 
 ## Output Format (--all Mode)
@@ -215,6 +228,10 @@ Z-Extensions (Base):
 
 The `--all` flag can be combined with other options (`-e`, `-l`, `-j`, `-r`, etc.).
 
+Note: `--all` mode's `✓`/`✗` reflects only what `/proc/cpuinfo` reports directly; it does
+not (yet) mark derived extensions differently. Derived (parenthesized) display is a
+default-mode / `--explain` feature only.
+
 ---
 
 ## Output Format (--json Mode)
@@ -223,24 +240,27 @@ The `--all` flag can be combined with other options (`-e`, `-l`, `-j`, `-r`, etc
 
 ```json
 {
-  "isa": "rv64imafdcv_zicsr_zifencei_zba_zbb_sstc",
+  "isa": "rv64imafdcv_zicsr_zifencei_zba_zbb_zbs_sstc",
   "extensions": [
-    {"name": "I", "description": "Base Integer Instructions"},
-    {"name": "M", "description": "Integer Multiply/Divide"},
-    {"name": "A", "description": "Atomic Instructions"},
-    {"name": "F", "description": "Single-Precision Float"},
-    {"name": "D", "description": "Double-Precision Float"},
-    {"name": "C", "description": "Compressed (16-bit)"},
-    {"name": "V", "description": "Vector (SIMD)"}
+    {"name": "I", "description": "Base Integer Instructions", "derived": false},
+    {"name": "M", "description": "Integer Multiply/Divide", "derived": false},
+    {"name": "A", "description": "Atomic Instructions", "derived": false},
+    {"name": "F", "description": "Single-Precision Float", "derived": false},
+    {"name": "D", "description": "Double-Precision Float", "derived": false},
+    {"name": "C", "description": "Compressed (16-bit)", "derived": false},
+    {"name": "V", "description": "Vector (SIMD)", "derived": false},
+    {"name": "B", "description": "Bit Manipulation", "derived": true}
   ],
   "z_extensions": [
-    {"name": "Zicsr", "description": "CSR Instructions"},
-    {"name": "Zifencei", "description": "Instruction-Fetch Fence"},
-    {"name": "Zba", "description": "Address Generation"},
-    {"name": "Zbb", "description": "Basic Bit Manipulation"}
+    {"name": "Zicsr", "description": "CSR Instructions", "derived": false},
+    {"name": "Zifencei", "description": "Instruction-Fetch Fence", "derived": false},
+    {"name": "Zba", "description": "Address Generation", "derived": false},
+    {"name": "Zbb", "description": "Basic Bit Manipulation", "derived": false},
+    {"name": "Zbs", "description": "Single-bit Operations", "derived": false},
+    {"name": "Zmmul", "description": "Multiply Only (no Div)", "derived": true}
   ],
   "s_extensions": [
-    {"name": "Sstc", "description": "Supervisor Timer"}
+    {"name": "Sstc", "description": "Supervisor Timer", "derived": false}
   ],
   "vector": {
     "enabled": true,
@@ -268,6 +288,11 @@ The `--all` flag can be combined with other options (`-e`, `-l`, `-j`, `-r`, etc
 }
 ```
 
+`extensions`/`z_extensions`/`s_extensions` entries carry `"derived": true` for
+extensions inferred via implication/composition (issue #10) that `/proc/cpuinfo` did
+not report directly; reported entries have `"derived": false`. This is an additive
+field — existing consumers that only read `name`/`description` are unaffected.
+
 ### Error (on non-RISC-V)
 
 ```json
@@ -375,12 +400,15 @@ Total score: 1234
 
 Must include:
 - Program description: "RISC-V architecture information display tool"
+- A note explaining the parentheses notation for derived extensions (issue #10)
 - All options with short and long forms
 - Brief description of each option
 
 ```
 RISC-V architecture information display tool
 
+Extensions shown in parentheses, e.g. (B) or (Zmmul), were not reported directly by /proc/cpuinfo but are implied by other extensions that are present (e.g. Zba+Zbb+Zbs implies B).
+
 Usage: riscfetch [OPTIONS]
 
 Options:
@@ -444,7 +472,7 @@ Example: `riscfetch 0.2.0`
 
 ## Version
 
-- Spec version: 2.1
-- Last updated: 2026-09
+- Spec version: 2.2
+- Last updated: 2026-09-17
 - Based on RISC-V ISA spec version: 2026-09
 - Supports 103 Z-extensions and 48 S-extensions (151 total)
diff --git a/crates/riscfetch-cli/src/cli.rs b/crates/riscfetch-cli/src/cli.rs
@@ -2,7 +2,12 @@ use clap::Parser;
 
 #[derive(Parser, Debug)]
 #[command(name = "riscfetch")]
-#[command(author, version, about = "RISC-V architecture information display tool", long_about = None)]
+#[command(
+    author,
+    version,
+    about = "RISC-V architecture information display tool",
+    long_about = "RISC-V architecture information display tool\n\nExtensions shown in parentheses, e.g. (B) or (Zmmul), were not reported directly by /proc/cpuinfo but are implied by other extensions that are present (e.g. Zba+Zbb+Zbs implies B)."
+)]
 #[allow(clippy::struct_excessive_bools)]
 pub struct Args {
     /// Vendor logo (default, sifive, starfive, thead, milkv, sipeed, pine64, eswin, ultrarisc, kendryte, allwinner, espressif, spacemit, sophgo, wch)