feat: Update ISA extensions to latest spec (144→147)

README.ja.md

@@ -15,7 +15,7 @@ RISC-V システム情報ツール。ISA 拡張、hart 数、ハードウェア
 
 ## 特徴
 
-- **144 拡張に対応**（Z 拡張 98 種 + S 拡張 46 種）
+- **147 拡張に対応**（Z 拡張 100 種 + S 拡張 47 種）
 - **カテゴリ別表示**で見やすい出力
 - **13 種類のベンダーロゴ**（Pine64、WCH 含む）
 - スクリプト向け JSON 出力
@@ -50,7 +50,7 @@ sudo mv riscfetch-linux-riscv64 /usr/local/bin/riscfetch
 
 ```bash
 riscfetch              # 標準出力
-riscfetch -a           # 全144拡張を ✓/✗ で表示
+riscfetch -a           # 全147拡張を ✓/✗ で表示
 riscfetch -a -e        # 全拡張を説明付きで表示
 riscfetch -r           # RISC-V 固有情報のみ（OS、メモリ等を除外）
 riscfetch -e           # 各 ISA 拡張の説明を表示
@@ -92,7 +92,7 @@ User:       user@visionfive2
 |--------|------|
 | `-r, --riscv-only` | RISC-V 固有情報のみ表示（OS、メモリ、稼働時間を除外） |
 | `-e, --explain` | 各拡張の意味を表示 |
-| `-a, --all` | 全144拡張を ✓/✗ チェックマーク付きで表示 |
+| `-a, --all` | 全147拡張を ✓/✗ チェックマーク付きで表示 |
 | `-j, --json` | 機械可読な JSON 出力 |
 | `-b, --benchmark` | ISA 固有のベンチマーク |
 | `-l, --logo <VENDOR>` | ベンダーロゴ（下記参照） |

README.md

@@ -15,7 +15,7 @@ System information tool for RISC-V. Displays ISA extensions, hart count, hardwar
 
 ## Features
 
-- **144 extensions supported** (98 Z-extensions + 46 S-extensions)
+- **147 extensions supported** (100 Z-extensions + 47 S-extensions)
 - **Category-based display** for easy reading
 - **13 vendor logos** including Pine64 and WCH
 - JSON output for scripting
@@ -50,7 +50,7 @@ sudo mv riscfetch-linux-riscv64 /usr/local/bin/riscfetch
 
 ```bash
 riscfetch              # standard output
-riscfetch -a           # show all 144 extensions with ✓/✗
+riscfetch -a           # show all 147 extensions with ✓/✗
 riscfetch -a -e        # all extensions with descriptions
 riscfetch -r           # RISC-V info only (no OS, memory, etc.)
 riscfetch -e           # explain each ISA extension
@@ -92,7 +92,7 @@ User:       user@visionfive2
 |------|-------------|
 | `-r, --riscv-only` | Show only RISC-V specific info (exclude OS, memory, uptime) |
 | `-e, --explain` | Show meaning of each extension |
-| `-a, --all` | Show all 144 extensions with ✓/✗ checkmarks |
+| `-a, --all` | Show all 147 extensions with ✓/✗ checkmarks |
 | `-j, --json` | Machine-readable JSON output |
 | `-b, --benchmark` | ISA-specific benchmarks |
 | `-l, --logo <VENDOR>` | Vendor logo (see below) |

README.zh-CN.md

@@ -15,7 +15,7 @@ RISC-V 系统信息工具。显示 ISA 扩展、hart 数量、硬件 ID 等信
 
 ## 特性
 
-- **支持 144 种扩展**（98 种 Z 扩展 + 46 种 S 扩展）
+- **支持 147 种扩展**（100 种 Z 扩展 + 47 种 S 扩展）
 - **分类显示**便于阅读
 - **13 种厂商 logo**（包括 Pine64 和 WCH）
 - 脚本友好的 JSON 输出
@@ -50,7 +50,7 @@ sudo mv riscfetch-linux-riscv64 /usr/local/bin/riscfetch
 
 ```bash
 riscfetch              # 标准输出
-riscfetch -a           # 显示全部144个扩展，带 ✓/✗ 标记
+riscfetch -a           # 显示全部147个扩展，带 ✓/✗ 标记
 riscfetch -a -e        # 全部扩展带说明
 riscfetch -r           # 仅显示 RISC-V 特定信息（排除 OS、内存等）
 riscfetch -e           # 解释每个 ISA 扩展
@@ -92,7 +92,7 @@ User:       user@visionfive2
 |------|------|
 | `-r, --riscv-only` | 仅显示 RISC-V 特定信息（排除 OS、内存、运行时间） |
 | `-e, --explain` | 显示每个扩展的含义 |
-| `-a, --all` | 显示全部 144 种扩展，带 ✓/✗ 标记 |
+| `-a, --all` | 显示全部 147 种扩展，带 ✓/✗ 标记 |
 | `-j, --json` | 机器可读的 JSON 输出 |
 | `-b, --benchmark` | ISA 特定基准测试 |
 | `-l, --logo <VENDOR>` | 厂商 logo（见下文） |

crates/riscfetch-cli/SPEC.md

@@ -182,7 +182,7 @@ S-Extensions (Supervisor):
 
 ## Output Format (--all Mode)
 
-Shows ALL defined extensions (144 total) with checkmarks indicating support status:
+Shows ALL defined extensions (147 total) with checkmarks indicating support status:
 
 - `✓` (green, bold) = Supported by this CPU
 - `✗` (gray/dim) = Not supported
@@ -444,5 +444,5 @@ Example: `riscfetch 0.2.0`
 
 - Spec version: 2.1
 - Last updated: 2025-12
-- Based on RISC-V ISA spec version: 2025-11-26
-- Supports 98 Z-extensions and 46 S-extensions (144 total)
+- Based on RISC-V ISA spec version: 2026-04
+- Supports 100 Z-extensions and 47 S-extensions (147 total)

crates/riscfetch-core/SPEC.md

@@ -318,5 +318,5 @@ parse_extensions_compact("rv64gc") → "I M A F D C"  (not "G C")
 
 - Spec version: 2.0
 - Last updated: 2025-12
-- Based on RISC-V ISA spec version: 2025-11-26 (Unprivileged/Privileged)
-- Reference: LLVM 22.0 RISC-V extension support
+- Based on RISC-V ISA spec version: 2026-04 (Unprivileged/Privileged)
+- Reference: LLVM mainline RISC-V extension support

crates/riscfetch-core/src/extensions.rs

@@ -1,7 +1,7 @@
 //! RISC-V extension definitions
 //!
 //! This module contains the constant definitions for all supported RISC-V extensions.
-//! Based on RISC-V ISA specification (2025-11-26) and LLVM 22.0 support.
+//! Based on RISC-V ISA specification (2026-04) and LLVM mainline support.
 
 /// Standard extension definitions
 /// Format: (char, name, description)
@@ -68,15 +68,17 @@ pub const Z_EXTENSIONS: &[(&str, &str, &str, &str)] = &[
     ("zca", "Zca", "Compressed Base", "comp"),
     ("zcb", "Zcb", "Compressed Basic Ops", "comp"),
     ("zcd", "Zcd", "Compressed Double FP", "comp"),
+    ("zce", "Zce", "Compressed for Embedded", "comp"),
     ("zcf", "Zcf", "Compressed Single FP", "comp"),
+    ("zclsd", "Zclsd", "Compressed LD/SD Pair", "comp"),
+    ("zcmop", "Zcmop", "Compressed May-Be-Ops", "comp"),
     ("zcmp", "Zcmp", "Compressed Push/Pop", "comp"),
     ("zcmt", "Zcmt", "Compressed Table Jump", "comp"),
-    ("zcmop", "Zcmop", "Compressed May-Be-Ops", "comp"),
-    ("zclsd", "Zclsd", "Compressed LD/SD Pair", "comp"),
     // Atomics
-    ("zacas", "Zacas", "Atomic Compare-and-Swap", "atomic"),
-    ("zabha", "Zabha", "Atomic Byte/Halfword", "atomic"),
     ("zaamo", "Zaamo", "Atomic AMO Subset", "atomic"),
+    ("zabha", "Zabha", "Atomic Byte/Halfword", "atomic"),
+    ("zacas", "Zacas", "Atomic Compare-and-Swap", "atomic"),
+    ("zalasr", "Zalasr", "Load-Acquire/Store-Release", "atomic"),
     ("zalrsc", "Zalrsc", "Atomic LR/SC Subset", "atomic"),
     ("zawrs", "Zawrs", "Wait-on-Reservation-Set", "atomic"),
     // Memory Model
@@ -146,6 +148,7 @@ pub const S_EXTENSIONS: &[(&str, &str, &str, &str)] = &[
     ("svade", "Svade", "A/D Update on Fault", "vm"),
     ("svadu", "Svadu", "A/D Hardware Update", "vm"),
     ("svbare", "Svbare", "Bare Translation Mode", "vm"),
+    ("svrsw60t59b", "Svrsw60t59b", "PTE Bits 60-59 for SW", "vm"),
     ("svvptc", "Svvptc", "VPTC Invalidation", "vm"),
     // Supervisor (Ss*)
     ("ssaia", "Ssaia", "Adv Interrupt Arch", "sup"),