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3 changes: 1 addition & 2 deletions cpu/lib/TritonCPUToLLVM/DotOpToLLVM.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -49,8 +49,7 @@ class GenericFMAVectorMultiplier : public triton::gpu::FMAVectorMultiplier {
}

// Multiply and accumulate.
auto mul = LLVM::FMulOp::create(builder, loc, tgtTy, aElem, bElem);
accum = LLVM::FAddOp::create(builder, loc, tgtTy, accum, mul);
accum = LLVM::FMAOp::create(builder, loc, tgtTy, aElem, bElem, accum);
}
return accum;
}
Expand Down
6 changes: 2 additions & 4 deletions test/Conversion/dot.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -13,8 +13,7 @@ module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 1 : i32, ttg.shar
// COM: We should see a bunch of repetitions of this pattern:
// CHECK: [[A:%.*]] = llvm.fpext {{%.*}} : f16 to f32
// CHECK: [[B:%.*]] = llvm.fpext {{%.*}} : f16 to f32
// CHECK: [[MUL:%.*]] = llvm.fmul [[A]], [[B]] : f32
// CHECK: {{%.*}} = llvm.fadd {{%.*}}, [[MUL]] : f32
// CHECK: [[MUL:%.*]] = llvm.intr.fma([[A]], [[B]], {{%.*}}) : (f32, f32, f32) -> f32
tt.return %d : tensor<2x2xf32, #blocked>
}
}
Expand All @@ -34,8 +33,7 @@ module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 1 : i32, ttg.shar
// COM: We should see a bunch of repetitions of this pattern:
// CHECK: [[A:%.*]] = llvm.fpext {{%.*}} : bf16 to f32
// CHECK: [[B:%.*]] = llvm.fpext {{%.*}} : bf16 to f32
// CHECK: [[MUL:%.*]] = llvm.fmul [[A]], [[B]] : f32
// CHECK: {{%.*}} = llvm.fadd {{%.*}}, [[MUL]] : f32
// CHECK: [[MUL:%.*]] = llvm.intr.fma([[A]], [[B]], {{%.*}}) : (f32, f32, f32) -> f32
tt.return %d : tensor<2x2xf32, #blocked>
}
}