A VHDL Mealy FSM that detects a sequence of 15 consecutive '0's followed by a sequence of 17 consecutive '1's.
The mealy FSM has three states:
- S0 (UNIT) : The state of waiting for the first '0'.
- S1 (FIRST): The state of
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A VHDL Mealy FSM that detects a sequence of 15 consecutive '0's followed by a sequence of 17 consecutive '1's.
The mealy FSM has three states: