Amaranth-GOWIN

Abstraction of Gowin primitives/IP cores for Amaranth HDL.

High-level PLL/PLLA abstraction (amaranth_gowin.pll)

from amaranth import *
from amaranth_gowin.pll import PLL

class MyModule(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        # Create a PLL with 60 MHz input and two outputs: 60 MHz and 240 MHz
        m.submodules.pll = pll = PLL(fclkin=60e6, outputs=[60e6, 240e6])
        m.d.comb += pll.clkin.eq(ClockSignal()

        m.domains += ClockDomain("pll60")
        m.d.comb += [
            ClockSignal("pll60").eq(pll.clkout[0]),
            ResetSignal("pll60").eq(~pll.lock)
        ]

        return m